{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T08:49:35Z","timestamp":1725612575169},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,3]]},"DOI":"10.1109\/date.2010.5456962","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T18:16:33Z","timestamp":1361297793000},"page":"1035-1040","source":"Crossref","is-referenced-by-count":1,"title":["Pareto efficient design for reconfigurable streaming applications on CPU\/FPGAs"],"prefix":"10.1109","author":[{"family":"Jun Zhu","sequence":"first","affiliation":[]},{"given":"Ingo","family":"Sander","sequence":"additional","affiliation":[]},{"given":"Axel","family":"Jantsch","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"Buffer sizing for rate-optimal single-rate dataflow scheduling revisited","author":"moreira","year":"2009","journal-title":"IEEE Trans Comput"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1289927.1289941"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1023\/B:TIME.0000016129.97430.c6"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337556"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MEMCOD.2006.1695924"},{"year":"0","key":"ref15","article-title":"Xilinx Ltd."},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2008.39"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ESTMED.2008.4696995"},{"key":"ref18","first-page":"1506","article-title":"Buffer minimization of real-time streaming applications scheduling on hybrid CPU\/FPGA architectures","author":"zhu","year":"2009","journal-title":"Proceedings of the Design Automation and Test in Europe (DATE)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/78.485935"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008052406396"},{"year":"2009","key":"ref6","article-title":"Gecode. Generic Constraint Development Environment"},{"journal-title":"Computers and Intractability A Guide to the Theory of NP-Completeness Freeman","year":"1979","author":"garey","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2005.193928"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364605"},{"key":"ref2","first-page":"44","article-title":"A reconfigurable computing primer","author":"barr","year":"1998","journal-title":"Multimedia System Design"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2004.36"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1987.5009446"}],"event":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","start":{"date-parts":[[2010,3,8]]},"location":"Dresden","end":{"date-parts":[[2010,3,12]]}},"container-title":["2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5450668\/5456897\/05456962.pdf?arnumber=5456962","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T19:26:43Z","timestamp":1489865203000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5456962\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,3]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/date.2010.5456962","relation":{},"subject":[],"published":{"date-parts":[[2010,3]]}}}