{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:40:24Z","timestamp":1761648024343,"version":"3.28.0"},"reference-count":28,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,3]]},"DOI":"10.1109\/date.2010.5457061","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T13:16:33Z","timestamp":1361279793000},"page":"1572-1577","source":"Crossref","is-referenced-by-count":17,"title":["Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors"],"prefix":"10.1109","author":[{"given":"Pramod","family":"Subramanyan","sequence":"first","affiliation":[]},{"given":"Virendra","family":"Singh","sequence":"additional","affiliation":[]},{"given":"Kewal K","family":"Saluja","sequence":"additional","affiliation":[]},{"given":"Erik","family":"Larsson","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2005.15"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1147\/rd.483.0519"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2008.12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1261390"},{"journal-title":"SESC Simulator","year":"2005","author":"renau","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2002.8"},{"key":"ref16","article-title":"Effects of Pipeline Complexity on SMT\/CMP Power-Performance Efficiency","author":"lee","year":"2005","journal-title":"Workshop on Complexity-Effective Design in conjunction with ISCA-30"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1147\/rd.494.0555"},{"key":"ref18","article-title":"Detailed Design and Evaluation of Redundant Multithreading Alternatives","author":"mukherjee","year":"2002","journal-title":"Proc of 29th ISCA"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1289881.1289923"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003565"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.110"},{"key":"ref27","article-title":"CACTI 5.1. Technical Report HPL-2008&#x2013;20","author":"thoziyoor","year":"0","journal-title":"HP Labs"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2005.70"},{"key":"ref6","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2007.100"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2004.72"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"ref2","article-title":"Reliable Systems on Unreliable Fabrics","volume":"25","author":"todd","year":"2008","journal-title":"IEEE Des Test"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.42"},{"key":"ref1","article-title":"Configurable isolation: building high availability systems with commodity multi-core processors","author":"nidhi","year":"2007","journal-title":"ISCA '07 Proc of the 34th ISCA"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555769"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1999.781037"},{"key":"ref21","first-page":"25","article-title":"Transient fault detection via simultaneous multithreading","author":"reinhardt","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2002.1028924"},{"key":"ref23","article-title":"Characterizing the Voltage Scaling Limitations of Razor-based Designs","author":"sartori","year":"2009","journal-title":"Workshop on Energy Effective Design"},{"key":"ref26","article-title":"Power-efficient redundant execution for chip multiprocessors","author":"subramanyan","year":"2009","journal-title":"Proceedings of 3rd WDSN"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379244"}],"event":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","start":{"date-parts":[[2010,3,8]]},"location":"Dresden","end":{"date-parts":[[2010,3,12]]}},"container-title":["2010 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE 2010)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5450668\/5456897\/05457061.pdf?arnumber=5457061","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T22:26:35Z","timestamp":1489875995000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5457061\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,3]]},"references-count":28,"URL":"https:\/\/doi.org\/10.1109\/date.2010.5457061","relation":{},"subject":[],"published":{"date-parts":[[2010,3]]}}}