{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T20:34:00Z","timestamp":1771706040794,"version":"3.50.1"},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,3]]},"DOI":"10.1109\/date.2010.5457072","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T18:16:33Z","timestamp":1361297793000},"page":"1629-1632","source":"Crossref","is-referenced-by-count":22,"title":["An analytical method for evaluating Network-on-Chip performance"],"prefix":"10.1109","author":[{"given":"Sahar","family":"Foroutan","sequence":"first","affiliation":[]},{"given":"Yvain","family":"Thonnart","sequence":"additional","affiliation":[]},{"given":"Richard","family":"Hersemeule","sequence":"additional","affiliation":[]},{"given":"Ahmed","family":"Jerraya","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"650","article-title":"An analytical model for wormhole routing in multicomputerinterconnection networks","author":"guan","year":"1993"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364440"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/12.53599"},{"key":"ref13","first-page":"547","article-title":"A General Analytical Model of Adaptive Wormhole Routing in k-Ary n-Cube Interconnection Networks","volume":"35","author":"khonsari","year":"2003","journal-title":"Simulation Series"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1155\/2007\/90941"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2007.4341515"},{"key":"ref16","author":"dally","year":"2004","journal-title":"Principles and Practices of Interconnection Networks"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2007.4341515"},{"key":"ref4","doi-asserted-by":"crossref","DOI":"10.1201\/9781420044720","author":"coppola","year":"2008","journal-title":"Design of Cost-Efficient Interconnect Processing Units Spidergon STNoC"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2005.10"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268972"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2002.1106819"},{"key":"ref8","first-page":"549","article-title":"An analytical model for wormhole routing with finite size input buffers","author":"hu","year":"1997"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364439"},{"key":"ref2","article-title":"The MANGO Clockless Network-on-Chip: Concepts and Implementation","author":"bjerregaard","year":"2005"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.99"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/PDP.2008.83"}],"event":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","location":"Dresden","start":{"date-parts":[[2010,3,8]]},"end":{"date-parts":[[2010,3,12]]}},"container-title":["2010 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE 2010)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5450668\/5456897\/05457072.pdf?arnumber=5457072","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T07:48:25Z","timestamp":1498031305000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5457072\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,3]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/date.2010.5457072","relation":{},"subject":[],"published":{"date-parts":[[2010,3]]}}}