{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,8]],"date-time":"2025-10-08T15:04:32Z","timestamp":1759935872282,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,3]]},"DOI":"10.1109\/date.2010.5457174","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T13:16:33Z","timestamp":1361279793000},"page":"387-392","source":"Crossref","is-referenced-by-count":4,"title":["Application-specific memory performance of a heterogeneous reconfigurable architecture"],"prefix":"10.1109","author":[{"given":"Sean","family":"Whitty","sequence":"first","affiliation":[]},{"given":"Henning","family":"Sahlbach","sequence":"additional","affiliation":[]},{"given":"Brady","family":"Hurlburt","sequence":"additional","affiliation":[]},{"given":"Rolf","family":"Ernst","sequence":"additional","affiliation":[]},{"given":"Wolfram","family":"Putzke-Roming","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2007.4380681"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-90-481-2427-5"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/76.246088"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364559"},{"key":"ref11","doi-asserted-by":"crossref","DOI":"10.5594\/M00404","article-title":"Motion compensated spatial-temporal reduction of film grain noise in the wavelet domain","author":"eichner","year":"2005","journal-title":"SMPTF Tech Conf"},{"key":"ref5","article-title":"PACT XPP-A Self-Reconfigurable Data Processing Architecture","author":"baumgarte","year":"2004","journal-title":"The Journal of Supercomputing"},{"key":"ref12","first-page":"15","article-title":"A High-End Real-Time Digital Film Processing Reconfigurable Platform","volume":"2007","author":"heithecker","year":"2007","journal-title":"EURASIP Journal on Embedded Systems Special Issue on Dynamically Reconfigurable Architectures"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090628"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSOC.2004.1411133"},{"journal-title":"ARM Ltd PrimeCell MultiPort Memory Controller (PL175) ARM Ltd","year":"2003","key":"ref2"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2008.4536536"},{"article-title":"Communication and Memory Scheduling in Reconfigurable Image Processing Systems","year":"2008","author":"heithecker","key":"ref9"}],"event":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","start":{"date-parts":[[2010,3,8]]},"location":"Dresden","end":{"date-parts":[[2010,3,12]]}},"container-title":["2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5450668\/5456897\/05457174.pdf?arnumber=5457174","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T03:48:23Z","timestamp":1498016903000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5457174\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,3]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/date.2010.5457174","relation":{},"subject":[],"published":{"date-parts":[[2010,3]]}}}