{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,4]],"date-time":"2025-11-04T15:55:14Z","timestamp":1762271714743,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,3]]},"DOI":"10.1109\/date.2010.5457197","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T18:16:33Z","timestamp":1361297793000},"page":"271-274","source":"Crossref","is-referenced-by-count":4,"title":["Energy-performance design space exploration in SMT architectures exploiting selective load value predictions"],"prefix":"10.1109","author":[{"given":"A","family":"Gellert","sequence":"first","affiliation":[]},{"given":"G","family":"Palermo","sequence":"additional","affiliation":[]},{"given":"V","family":"Zaccaria","sequence":"additional","affiliation":[]},{"given":"A","family":"Florea","sequence":"additional","affiliation":[]},{"given":"L","family":"Vintan","sequence":"additional","affiliation":[]},{"given":"C","family":"Silvano","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2008.11.002"},{"key":"ref11","first-page":"677","volume":"31","author":"wilton","year":"1996","journal-title":"CACTI An Enhanced Cache Access and Cycle Time Model"},{"key":"ref12","article-title":"M-sim: a flexible, multithreaded architectural simulation environment","author":"sharkey","year":"2005","journal-title":"Technical Report CS-TR-05-DPOl Department of Computer Science State University of New York at Binghamton"},{"key":"ref13","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"journal-title":"Evaluating future microprocessors The simplescalar tool set Technical Report CS-TR-1996-1308","year":"1996","author":"burger","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/2.869367"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/514191.514201"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45716-X_38"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765940"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20045090"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/782814.782859"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1138035.1138038"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/237090.237173"},{"journal-title":"Computer Architecture A Quantitative Approach","year":"1996","author":"patterson","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.22"}],"event":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","start":{"date-parts":[[2010,3,8]]},"location":"Dresden","end":{"date-parts":[[2010,3,12]]}},"container-title":["2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5450668\/5456897\/05457197.pdf?arnumber=5457197","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T19:29:40Z","timestamp":1489865380000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5457197\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,3]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/date.2010.5457197","relation":{},"subject":[],"published":{"date-parts":[[2010,3]]}}}