{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T15:41:57Z","timestamp":1725810117334},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,3]]},"DOI":"10.1109\/date.2010.5457210","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T13:16:33Z","timestamp":1361279793000},"page":"214-219","source":"Crossref","is-referenced-by-count":20,"title":["Memory testing with a RISC microcontroller"],"prefix":"10.1109","author":[{"given":"Ad","family":"van de Goor","sequence":"first","affiliation":[]},{"given":"Georgi","family":"Gaydadjiev","sequence":"additional","affiliation":[]},{"given":"Said","family":"Hamdioui","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"Memory Testing with a CISC Microcontroller","author":"van de goor","year":"2010","journal-title":"Submitted to DDECS conf"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DELTA.2002.994601"},{"key":"ref12","first-page":"66","article-title":"Logical and Topological Testing of Scrambled SRAMs","author":"schanstra","year":"2003","journal-title":"12th IEEE Latin American Test Workshop"},{"key":"ref13","first-page":"997","article-title":"A Modular Wrapper Enabling High Speed BISTand Repair for Small Wide Memories","author":"aitken","year":"2004","journal-title":"Int Test Conf"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894234"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2005.1584048"},{"key":"ref3","first-page":"45.3","article-title":"Full-Speed Field-Programmable Memory BIST Architecture","author":"du","year":"0","journal-title":"IEEE Int Test Conf paper"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2005.1583992"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1270862"},{"journal-title":"Testing Semiconductor Memories Theory and Practice","year":"1998","author":"van de goor","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2006.297673"},{"year":"0","key":"ref2"},{"year":"0","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-006-7761-1"}],"event":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","start":{"date-parts":[[2010,3,8]]},"location":"Dresden","end":{"date-parts":[[2010,3,12]]}},"container-title":["2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5450668\/5456897\/05457210.pdf?arnumber=5457210","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T22:10:28Z","timestamp":1489875028000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5457210\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,3]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/date.2010.5457210","relation":{},"subject":[],"published":{"date-parts":[[2010,3]]}}}