{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T15:04:38Z","timestamp":1730214278257,"version":"3.28.0"},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/date.2011.5763018","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T17:45:16Z","timestamp":1361295916000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Cross-layer optimized placement and routing for FPGA soft error mitigation"],"prefix":"10.1109","author":[{"family":"Keheng Huang","sequence":"first","affiliation":[]},{"family":"Yu Hu","sequence":"additional","affiliation":[]},{"family":"Xiaowei Li","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/TVLSI.2007.909795"},{"key":"ref11","first-page":"517","article-title":"LUT-based FPGA Technology Mapping for Reliability","author":"pcong","year":"0","journal-title":"Proc of IEEE\/ACM Design Automatic Conference (DAC) 2010"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/TNS.2004.839516"},{"key":"ref13","article-title":"Principle of Economics","author":"mankiw","year":"2003","journal-title":"South-Wester College"},{"key":"ref14","first-page":"409","article-title":"Test Pattern Generation for Multiple Output Digital Circuit using Cubical Calculus and Boolean Differences","volume":"1","author":"takhar","year":"1997","journal-title":"Proc IEEE Midwest Symp Circuits Systems"},{"year":"1980","author":"roth","article-title":"Computer Logic, Testing and Verification","key":"ref15"},{"key":"ref16","first-page":"194","article-title":"Device and Architecture Concurrent Optimization for FPGA Transient Soft Error Rate","author":"lin","year":"0","journal-title":"Proc of IEEE\/ACM Int Conference on Computer-Aided Design (ICCAD) 2007"},{"year":"2006","author":"wang","article-title":"VLSI Test Principles and Architectures","key":"ref17"},{"year":"0","article-title":"ABC: A system for sequential synthesis and verification","key":"ref18"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1109\/DAC.1983.1585651"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/TNS.2007.910426"},{"key":"ref3","first-page":"188","article-title":"Evaluating the effects of SEU's affecting the configuration memory of an SRAM-based FPGA","author":"bellato","year":"0","journal-title":"Proc of IEEE Design Automation and Test in Europe Conference and Exhibition (DATE) 2004"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/TNS.2005.860745"},{"key":"ref5","first-page":"c6.1","article-title":"Consequences and categories of SRAM FPGA configuration SEUs","author":"graham","year":"0","journal-title":"Proc of Military Aerospace Applications of Prgrammable Logic Devices (MAPLD) 2003"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/ISQED.2007.143"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/TC.2006.82"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/23.556861"},{"key":"ref1","first-page":"23","article-title":"Proton Testing of SEU Mitigation Methods for the Virtex FPGA","author":"carmichael","year":"0","journal-title":"Proc of the Military and Aerospace Applications of Prgrammable Lgic Devices (MAPLD) 1999"},{"key":"ref9","first-page":"330","article-title":"Single-Event-Upset (SEU) Awareness in FPGA Routing","author":"golshan","year":"0","journal-title":"Proc IEEE\/ACM Design Automation Conference (DAC) 2007"},{"key":"ref20","first-page":"213","article-title":"VPR: A New Packing, Placement and Routing Tool for FPGA Research","author":"betz","year":"0","journal-title":"Proc of IEEE Int Workshop on Field-Programmable Logic and Applications 1997"}],"event":{"name":"2011 Design, Automation & Test in Europe","start":{"date-parts":[[2011,3,14]]},"location":"Grenoble","end":{"date-parts":[[2011,3,18]]}},"container-title":["2011 Design, Automation &amp; Test in Europe"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5754459\/5762992\/05763018.pdf?arnumber=5763018","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T04:53:16Z","timestamp":1490071996000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5763018\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/date.2011.5763018","relation":{},"subject":[],"published":{"date-parts":[[2011,3]]}}}