{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T14:22:04Z","timestamp":1773843724360,"version":"3.50.1"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/date.2011.5763068","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T22:45:16Z","timestamp":1361313916000},"page":"1-6","source":"Crossref","is-referenced-by-count":50,"title":["Design space exploration for 3D-stacked DRAMs"],"prefix":"10.1109","author":[{"given":"C","family":"Weis","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N","family":"Wehn","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L","family":"Igor","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L","family":"Benini","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"1216","volume":"44","author":"klim","year":"2009","journal-title":"A 1 MB Cache Subsystem Prototype With 1 8 ns Embedded DRAMs in 45 nm SOI CMOS"},{"key":"ref11","year":"2010","journal-title":"Octopus 8-Port DRAM for Die-Stack Applications Data Sheet"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/4.509850"},{"key":"ref13","year":"2009","journal-title":"Databahn DRAM Memory Controller IP"},{"key":"ref14","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-031-01724-7","author":"jacob","year":"2009","journal-title":"The Memory System You Can't Avoid It You Can't Ignore It You Can't Fake It"},{"key":"ref15","year":"2009","journal-title":"1Gb x16 x32 Mobile Low-Power DDR SDRAM - Rev K 07\/09 EN Data sheet"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2009.5306600"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090797"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2009.4810274"},{"key":"ref6","article-title":"EuroCloud Project","year":"2010","journal-title":"Energy-conscious 3D Server-on-Chip for Green Cloud"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416628"},{"key":"ref8","first-page":"453","article-title":"3D-Stacked Memory Architectures for Multi-core Proces-sors","author":"loh","year":"0","journal-title":"ISCA '08 Proc of the 35th An Int Symp on Comp Arch"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457230"},{"key":"ref2","first-page":"38","article-title":"3d integration opportunities for memory interconnect in mobile computing architectures","author":"dutoit","year":"2010","journal-title":"Future Fab"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.105"}],"event":{"name":"2011 Design, Automation & Test in Europe","location":"Grenoble","start":{"date-parts":[[2011,3,14]]},"end":{"date-parts":[[2011,3,18]]}},"container-title":["2011 Design, Automation &amp; Test in Europe"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5754459\/5762992\/05763068.pdf?arnumber=5763068","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,6,29]],"date-time":"2023-06-29T17:07:08Z","timestamp":1688058428000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5763068\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/date.2011.5763068","relation":{},"subject":[],"published":{"date-parts":[[2011,3]]}}}