{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T08:11:43Z","timestamp":1729671103235,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/date.2011.5763106","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T17:45:16Z","timestamp":1361295916000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Clock gating optimization with delay-matching"],"prefix":"10.1109","author":[{"family":"Shih-Jung Hsu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Rung-Bin Lin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2030156"},{"article-title":"Method for Making Integrated Circuits Having Gated Clock Trees","year":"2003","author":"hathaway","key":"ref11"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"715","DOI":"10.1109\/43.924825","article-title":"Gated Clock Routing for Low-Power Microprocessor Design","volume":"20","author":"oh","year":"2001","journal-title":"IEEE Trans on CAD"},{"article-title":"Clock Gating Cell for Used in a Cell Library","year":"2003","author":"cheung","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391653"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"415","DOI":"10.1109\/81.841927","article-title":"Clock Gating and Its Application to Low Power Design of Sequential Circuits","volume":"47","author":"wu","year":"2000","journal-title":"IEEE Trans on circuits and systems - I Fundamental Theory and Applications"},{"article-title":"Reducing Clock Skew in Clock Gating Circuits","year":"2006","author":"borkovic","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629957"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/SOCDC.2009.5423918"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1297666.1297686"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/43.924824"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.1999.745123"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/43.503933"},{"key":"ref9","first-page":"176","article-title":"Challenges in Clock Gating for a Low Power ASIC Methodology","author":"garret","year":"2002","journal-title":"ISLPED"}],"event":{"name":"2011 Design, Automation & Test in Europe","start":{"date-parts":[[2011,3,14]]},"location":"Grenoble","end":{"date-parts":[[2011,3,18]]}},"container-title":["2011 Design, Automation & Test in Europe"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5754459\/5762992\/05763106.pdf?arnumber=5763106","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T03:50:06Z","timestamp":1498017006000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5763106\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/date.2011.5763106","relation":{},"subject":[],"published":{"date-parts":[[2011,3]]}}}