{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T16:04:25Z","timestamp":1761581065625,"version":"3.28.0"},"reference-count":27,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/date.2011.5763109","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T17:45:16Z","timestamp":1361295916000},"page":"1-6","source":"Crossref","is-referenced-by-count":33,"title":["Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture"],"prefix":"10.1109","author":[{"given":"A","family":"Strano","sequence":"first","affiliation":[]},{"given":"C","family":"Go\u0301mez","sequence":"additional","affiliation":[]},{"given":"D","family":"Ludovici","sequence":"additional","affiliation":[]},{"given":"M","family":"Favalli","sequence":"additional","affiliation":[]},{"given":"M E","family":"Go\u0301mez","sequence":"additional","affiliation":[]},{"given":"D","family":"Bertozzi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/6.774966"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/TEST.2002.1041777"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/DATE.2007.364619"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/TEST.2005.1584020"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/VTS.2002.1011112"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/DFTVS.2005.45"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1109\/MCOM.2003.1232240"},{"key":"ref17","first-page":"131","article-title":"Testing Strategies for Network on Chip","author":"ubar","year":"2003","journal-title":"Network on Chip"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1109\/54.980050"},{"key":"ref19","doi-asserted-by":"crossref","first-page":"404","DOI":"10.1109\/MDT.2005.108","article-title":"Design; Synthesis and Test of Networks on Chips","volume":"22","year":"2005","journal-title":"IEEE Design and Test of Computers"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/ATS.2006.260967"},{"year":"2001","author":"lata","journal-title":"Self-Checking and Fault Tolerant Digital Design","key":"ref27"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/MM.2007.4378780"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/TEST.2003.1271109"},{"year":"0","author":"raik","journal-title":"Test Configurtions for Diagnosing Faulty Links in NoC Switches Proc ETS 2007","key":"ref5"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1049\/iet-cdt.2008.0096"},{"key":"ref7","first-page":"62","article-title":"Architecture of the Scalable Communications Core's Network on Chip","author":"iiitzky","year":"2007","journal-title":"IEEE Micro"},{"key":"ref2","article-title":"Utilizing NoC Switches as BIST-Structures in 2D Mesh Network-on-Chip","author":"petersen","year":"2000","journal-title":"Workshop on Future Interconnects and Networks on Chip"},{"key":"ref9","first-page":"812","article-title":"VICIS: A Reliable Network for Unreliable Silicon","author":"bertacco","year":"0","journal-title":"DAC 2009"},{"key":"ref1","first-page":"559","article-title":"Xpipes Lite: a Synthesis Oriented Design Library for Networks on Chips","author":"stergiou","year":"2005","journal-title":"DAC"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1109\/ISCAS.2009.5118263"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1109\/VTS.2006.22"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1109\/DATE.2006.244018"},{"key":"ref24","first-page":"460","article-title":"Efficient Implementation of Distributed Routing Algorithms for Nocs","volume":"3","author":"ro-drigo","year":"2009","journal-title":"IET CDT"},{"key":"ref23","doi-asserted-by":"crossref","first-page":"327","DOI":"10.1109\/TCAD.2002.807889","article-title":"Testing ASICs with Multiple Identical Cores","volume":"22","author":"wu","year":"2003","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"ref26","first-page":"35","article-title":"Addressing Manufacturing Challenges with Cost-Effective Fault Tolerant Routine","author":"rodrigo","year":"2010","journal-title":"NoCs 2010"},{"year":"0","journal-title":"Submitted paper under review","key":"ref25"}],"event":{"name":"2011 Design, Automation & Test in Europe","start":{"date-parts":[[2011,3,14]]},"location":"Grenoble","end":{"date-parts":[[2011,3,18]]}},"container-title":["2011 Design, Automation & Test in Europe"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5754459\/5762992\/05763109.pdf?arnumber=5763109","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T03:50:07Z","timestamp":1498017007000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5763109\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":27,"URL":"https:\/\/doi.org\/10.1109\/date.2011.5763109","relation":{},"subject":[],"published":{"date-parts":[[2011,3]]}}}