{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,4]],"date-time":"2026-04-04T22:06:07Z","timestamp":1775340367896,"version":"3.50.1"},"reference-count":29,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/date.2011.5763120","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T17:45:16Z","timestamp":1361295916000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Evaluating the potential of graphics processors for high performance embedded computing"],"prefix":"10.1109","author":[{"family":"Shuai Mu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Chenxi Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Ming Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Dongdong Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Maohua Zhu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Xiaoliang Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Xiang Xie","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Yangdong Deng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1188455.1188549"},{"key":"ref11","first-page":"609","article-title":"FFT and Convolution Performance in image Filtering on GPU","author":"cadik","year":"2006","journal-title":"Information Visualization"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2006.19"},{"key":"ref13","author":"pettersson","year":"2010","journal-title":"Radar Signal Processing with Graphics Processors"},{"key":"ref14","article-title":"GPU Performance Assessment with the HPEC Challenge","author":"kerr","year":"0","journal-title":"HPEC Workshop in MIT Lincoln Laboratory"},{"key":"ref15","article-title":"CUDA FFT Library","year":"0"},{"key":"ref16","article-title":"CUDA SDK","year":"0"},{"key":"ref17","author":"coate","year":"2004","journal-title":"Preliminary design review Feature-aided tracking for the PCA integrated radar-tracker application"},{"key":"ref18","first-page":"855","article-title":"An Efficient Fine-grained Parallel Genetic Algorithm Based on GPU-Accelerated","author":"ming","year":"0","journal-title":"Network and Parallel Computing Workshops"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-95978-6_14"},{"key":"ref28","article-title":"ADSP-TSI0l TigerSHARC 6U cPCI board","year":"0"},{"key":"ref4","article-title":"Wikipedia, FLOPS","year":"0"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1807167.1807206"},{"key":"ref3","year":"0","journal-title":"High Performance DSP TMS320C647x Multicore DSP"},{"key":"ref6","year":"0","journal-title":"CUDA Programming Guide for CUDA Toolkit 3 1 1"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919648"},{"key":"ref5","article-title":"NVidia Fermi Compute Architecture Whitepaper","year":"0"},{"key":"ref8","article-title":"GPGPU-Sim","year":"0"},{"key":"ref7","article-title":"HPEC Challenge Benchmark Suite","year":"0"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSSTA.2006.311811"},{"key":"ref9","article-title":"Fourier volume rendering on the GPU using a split-stream-FFT","author":"jansen","year":"0","journal-title":"Proc Vision Modeling and Visualization Workshop"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1002\/0470113952"},{"key":"ref20","first-page":"85","article-title":"High Performance Genetic Programming on GPU","year":"0","journal-title":"Proc of 2009 ICAC workshop on Bio-inspired algorithms for distributed systems"},{"key":"ref22","author":"gene","year":"1996","journal-title":"Matrix Computations"},{"key":"ref21","article-title":"Vector, signal and image processing library(VSIPL) 1.3 application programmer","author":"david","year":"2008","journal-title":"interface Technical report Georgia Tech Research Corporation"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2008.5214359"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1513895.1513904"},{"key":"ref26","first-page":"93","article-title":"IP routing processing with graphic processors","author":"mu","year":"0","journal-title":"Design Automation & Test in Europe Conference & Exhibition (DATE)"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2009.5161058"}],"event":{"name":"2011 Design, Automation & Test in Europe","location":"Grenoble","start":{"date-parts":[[2011,3,14]]},"end":{"date-parts":[[2011,3,18]]}},"container-title":["2011 Design, Automation & Test in Europe"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5754459\/5762992\/05763120.pdf?arnumber=5763120","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T05:24:36Z","timestamp":1490073876000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5763120\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1109\/date.2011.5763120","relation":{},"subject":[],"published":{"date-parts":[[2011,3]]}}}