{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,15]],"date-time":"2026-04-15T22:06:57Z","timestamp":1776290817771,"version":"3.50.1"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/date.2011.5763125","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T22:45:16Z","timestamp":1361313916000},"page":"1-6","source":"Crossref","is-referenced-by-count":38,"title":["Design implications of memristor-based RRAM cross-point structures"],"prefix":"10.1109","author":[{"family":"Cong Xu","sequence":"first","affiliation":[]},{"family":"Xiangyu Dong","sequence":"additional","affiliation":[]},{"given":"N P","family":"Jouppi","sequence":"additional","affiliation":[]},{"family":"Yuan Xie","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","first-page":"554","DOI":"10.1145\/1391469.1391610","article-title":"circuit and microarchitecture evaluation of 3d stacking magnetic ram (mram) as a universal memory replacement","author":"xiangyu dong","year":"2008","journal-title":"2008 45th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687449"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457154"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1038\/nmat2023"},{"key":"ref14","first-page":"37","article-title":"An access-transistor-free (0T\/1R) non-volatile resistance random access memory (RRAM) using a novel threshold switching, self-rectifying chalcogenide device","author":"chen","year":"2003","journal-title":"Proceedings of the International Electron Devices Meeting"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/4.75050"},{"key":"ref16","year":"2009","journal-title":"International Technology Roadmap for Semiconductors Process Inte-gration Devices and Structures"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2010.2041183"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1149\/1.3267050"},{"key":"ref6","first-page":"2008","author":"thoziyoor","year":"2008","journal-title":"CACTI 5 1 Technical Report"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MSPEC.2008.4687366"},{"key":"ref8","first-page":"4","author":"mamidipaka","year":"2004","journal-title":"eCACTI An enhanced power estimation model for on-chip caches"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/4.384170"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1038\/nature06932"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCT.1971.1083337"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.2"}],"event":{"name":"2011 Design, Automation & Test in Europe","location":"Grenoble","start":{"date-parts":[[2011,3,14]]},"end":{"date-parts":[[2011,3,18]]}},"container-title":["2011 Design, Automation & Test in Europe"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5754459\/5762992\/05763125.pdf?arnumber=5763125","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T07:50:04Z","timestamp":1498031404000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5763125\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/date.2011.5763125","relation":{},"subject":[],"published":{"date-parts":[[2011,3]]}}}