{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T22:04:28Z","timestamp":1725660268399},"reference-count":24,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/date.2011.5763157","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T17:45:16Z","timestamp":1361295916000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Flex memory: Exploiting and managing abundant off-chip optical bandwidth"],"prefix":"10.1109","author":[{"family":"Ying Wang","sequence":"first","affiliation":[]},{"family":"Lei Zhang","sequence":"additional","affiliation":[]},{"family":"Yinhe Han","sequence":"additional","affiliation":[]},{"family":"Huawei Li","sequence":"additional","affiliation":[]},{"family":"Xiaowei Li","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/DATE.2007.364438"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/ISSCC.2009.4977511"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/PHOTWTM.2010.5421931"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1145\/181181.181559"},{"key":"ref14","article-title":"Reducing DRAM Latencies with an Integrated Memory Hierarchy Design","author":"lin","year":"2001","journal-title":"Proc of the Int Symp on High-Performance Computing"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1145\/1736020.1736058"},{"key":"ref16","article-title":"Effective Management of DRAM Bandwidth in Multicore Processors","author":"rafique","year":"0","journal-title":"Proc of the 16th International Conference on Parallel Architectures and Compilation Techniques"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1109\/MICRO.2007.21"},{"key":"ref18","article-title":"Understanding How Off-Chip Memory Bandwidth Partitioning in Chip Multiprocessors Affects System Performance","author":"liu","year":"2010","journal-title":"HPCA"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1109\/MICRO.2006.24"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/MM.2007.18"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/HOTI.2008.11"},{"key":"ref6","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-031-01722-3","author":"barroso","year":"2009","journal-title":"The Datacenter as a Computer An Introduction to the Design of Warehouse-Scale Machines"},{"key":"ref5","first-page":"153","article-title":"Corona: System Implications of Emerging Nanophotonic Technology","author":"vantrease","year":"2008","journal-title":"ISCA 08 IEEE CS Press"},{"key":"ref8","first-page":"933","article-title":"Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs Design","author":"fu","year":"0","journal-title":"Design Automation & Test in Europe Conference & Exhibition (DATE"},{"key":"ref7","first-page":"175","article-title":"Optical Interconnects for Presentand Future High-Performance Computing Systems","author":"krishnamoorthy","year":"0","journal-title":"Proc Hot Interconnects (HOT I 08) IEEE CS Press"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1145\/1815961.1815978"},{"year":"2007","article-title":"ITRS. International Technology Roadmap for Semiconductors","key":"ref1"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/MM.2006.32"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1145\/1736020.1736045"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1109\/L-CA.2008.13"},{"key":"ref21","article-title":"Mini-Rank: Adaptive DRAMArchitecture For Improving Memory Power Efficiency","author":"zheng","year":"2008","journal-title":"Proceedings of MICRO"},{"doi-asserted-by":"publisher","key":"ref24","DOI":"10.1109\/ISCA.2008.15"},{"doi-asserted-by":"publisher","key":"ref23","DOI":"10.1145\/1815961.1815983"}],"event":{"name":"2011 Design, Automation & Test in Europe","start":{"date-parts":[[2011,3,14]]},"location":"Grenoble","end":{"date-parts":[[2011,3,18]]}},"container-title":["2011 Design, Automation &amp; Test in Europe"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5754459\/5762992\/05763157.pdf?arnumber=5763157","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,6,29]],"date-time":"2023-06-29T13:07:28Z","timestamp":1688044048000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5763157\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/date.2011.5763157","relation":{},"subject":[],"published":{"date-parts":[[2011,3]]}}}