{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T15:04:54Z","timestamp":1730214294364,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/date.2011.5763160","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T22:45:16Z","timestamp":1361313916000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Stability optimization of embedded 8T SRAMs using Word-Line Voltage modulation"],"prefix":"10.1109","author":[{"given":"B","family":"Alorda","sequence":"first","affiliation":[]},{"given":"G","family":"Torrens","sequence":"additional","affiliation":[]},{"given":"S","family":"Bota","sequence":"additional","affiliation":[]},{"given":"J","family":"Segura","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.842846"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.892153"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.917509"},{"key":"ref6","article-title":"A 45nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R\/W Access Issues","volume":"43","author":"akamatsu","year":"2008","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5433815"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2010.5450413"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2043462"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2020201"},{"key":"ref2","first-page":"129","article-title":"Analysing Static and Dynamic Write Margin for nanometers SRAMs","author":"wang","year":"0","journal-title":"Proc Int Symp Low Power Electronics Design"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457165"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052809"}],"event":{"name":"2011 Design, Automation & Test in Europe","start":{"date-parts":[[2011,3,14]]},"location":"Grenoble","end":{"date-parts":[[2011,3,18]]}},"container-title":["2011 Design, Automation & Test in Europe"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5754459\/5762992\/05763160.pdf?arnumber=5763160","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T09:09:26Z","timestamp":1490087366000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5763160\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/date.2011.5763160","relation":{},"subject":[],"published":{"date-parts":[[2011,3]]}}}