{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T21:05:26Z","timestamp":1725483926718},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/date.2011.5763198","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T17:45:16Z","timestamp":1361295916000},"page":"1-6","source":"Crossref","is-referenced-by-count":11,"title":["SHARC: A streaming model for FPGA accelerators and its application to Saliency"],"prefix":"10.1109","author":[{"given":"S","family":"Kestur","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D","family":"Dantara","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"V","family":"Narayanan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/370155.370532"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/34.730558"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1016\/j.neunet.2006.10.001"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.1994.323833"},{"journal-title":"ML605 Documentation","year":"0","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1279920.1279923"},{"key":"ref16","article-title":"A High-speed Multi-GPU Implementation of Bottom-up Attention using CUDA","author":"xu","year":"2009","journal-title":"Proc IEEE Int Conf Robot and Automat ICRA"},{"journal-title":"Intel Xeon","year":"0","key":"ref17"},{"journal-title":"GeForce 8 Series","year":"0","key":"ref18"},{"journal-title":"Virtex Data Sheet","year":"0","key":"ref19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1117\/12.834177"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272559"},{"journal-title":"LocalLink user interface","year":"0","key":"ref6"},{"journal-title":"FPGAs for Stream Processing A Natural Choice","year":"0","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457185"},{"journal-title":"Altera White Paper","article-title":"FPGA Run-time Reconfiguration: Two Approaches","year":"0","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2007.375295"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457096"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2010.5537908"}],"event":{"name":"2011 Design, Automation & Test in Europe","start":{"date-parts":[[2011,3,14]]},"location":"Grenoble","end":{"date-parts":[[2011,3,18]]}},"container-title":["2011 Design, Automation & Test in Europe"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5754459\/5762992\/05763198.pdf?arnumber=5763198","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T05:32:30Z","timestamp":1490074350000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5763198\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/date.2011.5763198","relation":{},"subject":[],"published":{"date-parts":[[2011,3]]}}}