{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:50:09Z","timestamp":1759146609224,"version":"3.28.0"},"reference-count":25,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/date.2011.5763226","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T22:45:16Z","timestamp":1361313916000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Power optimization in heterogenous datapaths"],"prefix":"10.1109","author":[{"given":"A A","family":"Del Barrio","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S O","family":"Memik","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M C","family":"Molina","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J M","family":"Mendias","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R","family":"Hermida","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2007.03.018"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/224081.224099"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"11","DOI":"10.1145\/764808.764812","article-title":"A Comprehensive HLS System for Control-Flow Intensive Behaviors","author":"wang","year":"2003","journal-title":"GLSVLSI"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.358038"},{"key":"ref14","first-page":"436","article-title":"A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits","author":"mukherjee","year":"2003","journal-title":"Proc 21st ICCD"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311288"},{"key":"ref16","first-page":"267","article-title":"Restricted Chaining and Fragmentation Techniques in Power Aware High-Level Synthesis","author":"del barrio","year":"2008","journal-title":"11 th Euromicro DSD"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"321","DOI":"10.1049\/ip-cdt:20030835","article-title":"Behavioural specification allocation to minimize bit level waste of functional units","volume":"150","author":"molina","year":"2003","journal-title":"Proc Inst Elect Eng -Comput Digit Tech"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852663"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1121058"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313937"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/505306.505317"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-008-0319-y"},{"key":"ref5","first-page":"602","article-title":"Low Power Multiplier with Bypassing and Tree Structure","author":"kuo","year":"2006","journal-title":"IEEE APCCAS"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1049\/el:20050464"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2006.1692877"},{"journal-title":"Low-Power High-Level Synthesis for Nanoscale CMOS","year":"2008","author":"mohanty","key":"ref2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICM.2005.1590040"},{"journal-title":"High-Level Synthesis from Algorithm to Circuit Design","year":"2008","author":"coussy","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1059876.1059883"},{"journal-title":"Computer Arithmetic Algorithms","year":"2002","author":"koren","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/92.845896"},{"journal-title":"Fundamentals of Algorithmics","year":"1996","author":"brassard","key":"ref24"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/43.31522"},{"key":"ref25","first-page":"768","article-title":"Algorithms for hardware allocation in data path synthesis","author":"devadas","year":"1999","journal-title":"IEEE Trans on CAD"}],"event":{"name":"2011 Design, Automation & Test in Europe","start":{"date-parts":[[2011,3,14]]},"location":"Grenoble","end":{"date-parts":[[2011,3,18]]}},"container-title":["2011 Design, Automation &amp; Test in Europe"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5754459\/5762992\/05763226.pdf?arnumber=5763226","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,5,6]],"date-time":"2024-05-06T07:09:16Z","timestamp":1714979356000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5763226\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/date.2011.5763226","relation":{},"subject":[],"published":{"date-parts":[[2011,3]]}}}