{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:57:43Z","timestamp":1759147063484,"version":"3.28.0"},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/date.2011.5763249","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T17:45:16Z","timestamp":1361295916000},"page":"1-6","source":"Crossref","is-referenced-by-count":5,"title":["Aging-aware timing analysis and optimization considering path sensitization"],"prefix":"10.1109","author":[{"family":"Kai-Chiang Wu","sequence":"first","affiliation":[]},{"given":"D","family":"Marculescu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2006.4380820"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.48"},{"key":"ref12","first-page":"370","article-title":"NBTI-aware synthesis of digital circuits","author":"kumar","year":"2007","journal-title":"Proc ofDAC"},{"key":"ref13","first-page":"75","article-title":"Joint logic restructuring and pin reordering against NBTI-induced performance degradation","author":"wu","year":"2009","journal-title":"Proc of DATE"},{"key":"ref14","first-page":"244","article-title":"Aging-resilient design of pipelined architectures using novel detecti on and correction circuits","author":"dadgour","year":"0","journal-title":"Proc of DATE"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364650"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090649"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/43.205000"},{"key":"ref18","first-page":"735","article-title":"An efficient method to identify critical gates under circuit aging","author":"wang","year":"2007","journal-title":"Proc of ICCAD"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/92.645073"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.2004.1315337"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2005.08.001"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233601"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.1999.799346"},{"key":"ref8","first-page":"417","article-title":"Efficient Boolean characteristic function for timed automatic test pattern generation","volume":"28","author":"kuo","year":"2009","journal-title":"IEEE TCAD"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2008810"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1063\/1.1567461"},{"journal-title":"International Technology Roadmap for Semiconductor","year":"2009","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.244119"}],"event":{"name":"2011 Design, Automation & Test in Europe","start":{"date-parts":[[2011,3,14]]},"location":"Grenoble","end":{"date-parts":[[2011,3,18]]}},"container-title":["2011 Design, Automation &amp; Test in Europe"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5754459\/5762992\/05763249.pdf?arnumber=5763249","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T05:01:32Z","timestamp":1490072492000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5763249\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/date.2011.5763249","relation":{},"subject":[],"published":{"date-parts":[[2011,3]]}}}