{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:57:59Z","timestamp":1759147079172,"version":"3.28.0"},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/date.2011.5763264","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T22:45:16Z","timestamp":1361313916000},"page":"1-4","source":"Crossref","is-referenced-by-count":6,"title":["Automated constraint-driven topology synthesis for analog circuits"],"prefix":"10.1109","author":[{"given":"O","family":"Mitea","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M","family":"Meissner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L","family":"Hedrich","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P","family":"Jores","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TEVC.2004.841308"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090756"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1118299.1118463"},{"key":"ref13","first-page":"4","article-title":"Hierarchical exploration and selection of transistor-topologies for analog circuit design","author":"wang","year":"2006","journal-title":"Circuits and Systems 2006 ISCAS 2006 Proceedings 2006 IEEE International Symposium on"},{"year":"0","author":"muneda","key":"ref14"},{"journal-title":"Design of Analog CMOS Integrated Circuits","year":"2000","author":"razavi","key":"ref15"},{"journal-title":"The Sizing Rules Method for Analog Integrated Circuit Design","year":"2001","author":"graeb","key":"ref16"},{"journal-title":"Cadence Design Framework II","year":"0","key":"ref17"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/92.386223"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"113","DOI":"10.1109\/43.46777","article-title":"OPASYN: A compiler for CMOS operational amplifiers","volume":"9","author":"hykohsequin","year":"1990","journal-title":"Computer-Aided Design of Integrated Circuits and Systems IEEE Transactions on"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/43.372366"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/43.44506"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/4235.996017"},{"key":"ref7","first-page":"433","article-title":"DARWIN: CMOS opamp synthesis by means of a genetic algorithm","author":"kruiskamp","year":"2006","journal-title":"Design Automation 1995 DAC '95 32nd Conference on"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1990.112108"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233593"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391483"}],"event":{"name":"2011 Design, Automation & Test in Europe","start":{"date-parts":[[2011,3,14]]},"location":"Grenoble","end":{"date-parts":[[2011,3,18]]}},"container-title":["2011 Design, Automation &amp; Test in Europe"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5754459\/5762992\/05763264.pdf?arnumber=5763264","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T07:50:05Z","timestamp":1498031405000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5763264\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/date.2011.5763264","relation":{},"subject":[],"published":{"date-parts":[[2011,3]]}}}