{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T19:00:02Z","timestamp":1771700402122,"version":"3.50.1"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/date.2011.5763278","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T17:45:16Z","timestamp":1361295916000},"page":"1-4","source":"Crossref","is-referenced-by-count":3,"title":["An energy-efficient 3D CMP design with fine-grained voltage scaling"],"prefix":"10.1109","author":[{"family":"Jishen Zhao","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Xiangyu Dong","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Yuan Xie","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"ref11","year":"0"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1997.585445"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"ref14","year":"0","journal-title":"SPEC OMP2001"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798259"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"148","DOI":"10.1145\/545214.545232","article-title":"Drowsy caches: simple techniques for reducing leakage power","author":"flautner","year":"2002","journal-title":"Proceedings of the International Symposium on Computer Architecture"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1148015.1148016"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.134"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555793"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.842837"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268819"},{"key":"ref1","first-page":"222","article-title":"Variation-tolerant nonuniform 3D cache management in die stacked multicore processor","author":"zhao","year":"0","journal-title":"International Symposium on Microarchitecture 2009"},{"key":"ref9","first-page":"1","article-title":"System level analysis of fast, per-core DVFS using on-chip switching regulators","author":"kim","year":"2008","journal-title":"Proceedings of the International Conference on High-Performance Computer Architecture"}],"event":{"name":"2011 Design, Automation & Test in Europe","location":"Grenoble","start":{"date-parts":[[2011,3,14]]},"end":{"date-parts":[[2011,3,18]]}},"container-title":["2011 Design, Automation &amp; Test in Europe"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5754459\/5762992\/05763278.pdf?arnumber=5763278","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,7,9]],"date-time":"2019-07-09T18:44:05Z","timestamp":1562697845000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5763278\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/date.2011.5763278","relation":{},"subject":[],"published":{"date-parts":[[2011,3]]}}}