{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T05:28:38Z","timestamp":1747805318980},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/date.2011.5763300","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T17:45:16Z","timestamp":1361295916000},"page":"1-4","source":"Crossref","is-referenced-by-count":3,"title":["Transition-Time-Relation based capture-safety checking for at-speed scan test generation"],"prefix":"10.1109","author":[{"given":"K","family":"Miyase","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"X","family":"Wen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M","family":"Aso","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H","family":"Furukawa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Y","family":"Yamato","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S","family":"Kajihara","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Low-Power Testing (Chapter 7) in Advanced SOC Test Architectures - Towards Nanometer Designs","year":"2007","author":"girard","key":"ref4"},{"journal-title":"Power-Aware Testing and Test Strategies for Low Power Devices","year":"2009","author":"girard","key":"ref3"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2007.375221"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2007.4437596"},{"key":"ref11","first-page":"533","article-title":"Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design","author":"ahmed","year":"2007","journal-title":"Proc Design Automation Conf"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VDAT.2009.5158160"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/127601.127729"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2007.101"},{"key":"ref7","first-page":"265","article-title":"On Low-Capture-Power Test Generation for Scan Testing","author":"wen","year":"2005","journal-title":"Proc VLSI Test Symp"},{"key":"ref2","first-page":"17","article-title":"High-Frequency, At-Speed Scan Testing","author":"lin","year":"2003","journal-title":"IEEE Design & Test of Computers"},{"key":"ref9","article-title":"A Novel Architecture for On-Chip Path Delay Measurenent","author":"wang","year":"2009","journal-title":"Proc Int'l Test Conf Paper 12 1"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1993.313316"}],"event":{"name":"2011 Design, Automation & Test in Europe","start":{"date-parts":[[2011,3,14]]},"location":"Grenoble","end":{"date-parts":[[2011,3,18]]}},"container-title":["2011 Design, Automation &amp; Test in Europe"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5754459\/5762992\/05763300.pdf?arnumber=5763300","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T05:28:20Z","timestamp":1490074100000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5763300\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/date.2011.5763300","relation":{},"subject":[],"published":{"date-parts":[[2011,3]]}}}