{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T03:44:26Z","timestamp":1725767066250},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/date.2011.5763309","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T22:45:16Z","timestamp":1361313916000},"page":"1-4","source":"Crossref","is-referenced-by-count":3,"title":["jTLM: An experimentation framework for the simulation of transaction-level models of Systems-on-Chip"],"prefix":"10.1109","author":[{"given":"G","family":"Funchal","sequence":"first","affiliation":[]},{"given":"M","family":"Moy","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"Acc&#x00E9;l&#x00E9;ration des simulations de syst&#x00E8;mes-sur-puce an niveau transactionnel","author":"bouzouzou","year":"2007","journal-title":"Dipl&#x00F4;me de Recherche Technologique Universit&#x00E9; Joseph Fourier"},{"journal-title":"Separation of Functional and Non-Functional Aspects in Transactional Level Models of Systems-on-Chip","year":"2008","author":"cornet","key":"ref11"},{"key":"ref12","first-page":"41","article-title":"QEMU, a fast and portable dynamic translator","author":"bellard","year":"2005","journal-title":"Proc USENIX ATC"},{"journal-title":"User Mode Linux","year":"2006","author":"dike","key":"ref13"},{"journal-title":"JSR 133 Java Memory Model and Thread Specification","year":"2004","author":"microsystems","key":"ref14"},{"year":"2006","key":"ref4"},{"journal-title":"Transaction-Level Modeling With SystemC TLM Concepts and Applications for Embedded Systems","year":"2006","author":"ghenassia","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2008.4484652"},{"key":"ref5","first-page":"100","article-title":"Test coverage for loose timing annotations","author":"helmstetter","year":"2006","journal-title":"FMICS\/PDMC"},{"journal-title":"SpecC Language Reference Manual 2 0","year":"2002","author":"d\u00f6mer","key":"ref8"},{"journal-title":"JTLM an Experimentation Framework for the Simulation of transaction-level models of systems-on-chip","year":"2010","author":"funchal","key":"ref7"},{"journal-title":"Apple","year":"2010","key":"ref2"},{"journal-title":"Techniques and Tools for the Verification of Systems-on-a-Chip at the Transaction Level","year":"2005","author":"moy","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/11758549_89"}],"event":{"name":"2011 Design, Automation & Test in Europe","start":{"date-parts":[[2011,3,14]]},"location":"Grenoble","end":{"date-parts":[[2011,3,18]]}},"container-title":["2011 Design, Automation &amp; Test in Europe"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5754459\/5762992\/05763309.pdf?arnumber=5763309","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T11:08:35Z","timestamp":1490094515000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5763309\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/date.2011.5763309","relation":{},"subject":[],"published":{"date-parts":[[2011,3]]}}}