{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,8]],"date-time":"2025-04-08T23:32:45Z","timestamp":1744155165184},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,3]]},"DOI":"10.1109\/date.2012.6176651","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T13:16:29Z","timestamp":1361279789000},"page":"1054-1059","source":"Crossref","is-referenced-by-count":1,"title":["MAPG: Memory access power gating"],"prefix":"10.1109","author":[{"family":"Kwangok Jeong","sequence":"first","affiliation":[]},{"given":"A. B.","family":"Kahng","sequence":"additional","affiliation":[]},{"family":"Seokhyeong Kang","sequence":"additional","affiliation":[]},{"given":"T. S.","family":"Rosing","sequence":"additional","affiliation":[]},{"given":"R.","family":"Strong","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2007.4405859"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1145\/781027.781076"},{"journal-title":"Low Power Methodology Manual","year":"2007","author":"flynn","key":"17"},{"year":"2010","key":"18"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2011.29"},{"key":"16","first-page":"55","article-title":"SRAM Leakage Suppression by Minimizing Standby Supply Voltage","author":"qin","year":"0","journal-title":"Proc 2004 5th Int Symp Quality Electronic Design"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.894428"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2008.4541731"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/1594233.1594331"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749737"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.82"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/1835420.1835421"},{"year":"2011","author":"dobre","key":"20"},{"year":"2006","key":"2"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2004.1349303"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.904101"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.102"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-6388-8"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2009.46"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2009.4977306"},{"key":"8","first-page":"388","article-title":"A Power Gating Scheme for Ground Bounce Reduction during Mode Transition","author":"he","year":"0","journal-title":"Proc International Conference on Computer Design 2007"}],"event":{"name":"2012 Design, Automation & Test in Europe Conference & Exhibition (DATE 2012)","start":{"date-parts":[[2012,3,12]]},"location":"Dresden","end":{"date-parts":[[2012,3,16]]}},"container-title":["2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6171057\/6176405\/06176651.pdf?arnumber=6176651","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T15:26:24Z","timestamp":1490109984000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6176651\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,3]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/date.2012.6176651","relation":{},"subject":[],"published":{"date-parts":[[2012,3]]}}}