{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,4]],"date-time":"2025-11-04T10:25:28Z","timestamp":1762251928196},"reference-count":51,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,3]]},"DOI":"10.1109\/date.2012.6176689","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T13:16:29Z","timestamp":1361279789000},"page":"1277-1282","source":"Crossref","is-referenced-by-count":37,"title":["Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs"],"prefix":"10.1109","author":[{"given":"E. J.","family":"Marinissen","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"35","article-title":"Challenges and Solutions for Testing of TSV and Micro-Bump","author":"eldridge","year":"0","journal-title":"Digest of IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST) September 2011"},{"key":"36","article-title":"A Low-Force MEMS Probe Solution for Fine-Pitch 3D-SIC Wafer Test","author":"losey","year":"0","journal-title":"Digest of IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST) September 2011"},{"doi-asserted-by":"publisher","key":"33","DOI":"10.1109\/TEST.2004.1387391"},{"doi-asserted-by":"publisher","key":"34","DOI":"10.1109\/TEST.2011.6139180"},{"doi-asserted-by":"publisher","key":"39","DOI":"10.1109\/DATE.2009.5090751"},{"key":"37","article-title":"Wafer Probing on Fine-Pitch Micro-Bumps for 2.5D- and 3D-SICs","author":"tha?rigen","year":"0","journal-title":"Semicon European Manufacturing Test Conference (EMTC) October 2011"},{"doi-asserted-by":"publisher","key":"38","DOI":"10.1109\/TEST.2007.4437595"},{"doi-asserted-by":"publisher","key":"43","DOI":"10.1109\/TEST.2001.966695"},{"key":"42","article-title":"Wide-IO DRAM - ST-Ericsson's First Mobile Processor Using TSV 3D-IC Technology","author":"freund","year":"2011","journal-title":"CDNLive! EMEA"},{"key":"41","first-page":"496","article-title":"A 1.2V 12.8GB\/s 2Gb MobileWide-I\/O DRAM with 4x128 I\/Os Using TSV-Based Stacking","author":"kim","year":"2011","journal-title":"Proc Int l Solid-States Circuits Conf (ISSCC)"},{"doi-asserted-by":"publisher","key":"40","DOI":"10.1109\/ETS.2011.24"},{"doi-asserted-by":"publisher","key":"22","DOI":"10.1109\/VTS.2011.5783751"},{"doi-asserted-by":"publisher","key":"23","DOI":"10.1109\/MDT.2009.12"},{"doi-asserted-by":"publisher","key":"24","DOI":"10.1109\/ETS.2005.38"},{"doi-asserted-by":"publisher","key":"25","DOI":"10.1109\/MDT.2009.65"},{"key":"26","first-page":"161","article-title":"Design and Measurements of Test Element Group Wafer Thinned to 10?m for 3D System in Package","author":"ikeda","year":"2004","journal-title":"Proceedings IEEE International Conference on Microelectronic Test Structures"},{"key":"27","first-page":"282","article-title":"Impact of Thinning and Packaging on a Deep Sub-Micron CMOS Product","author":"perry","year":"2009","journal-title":"Electronic Workshop Digest of DATE 2009 Friday Workshop on 3D Integration"},{"doi-asserted-by":"publisher","key":"28","DOI":"10.1109\/ISSCC.2010.5434016"},{"doi-asserted-by":"publisher","key":"29","DOI":"10.1109\/CICC.2010.5617425"},{"doi-asserted-by":"publisher","key":"3","DOI":"10.1002\/9783527623051"},{"doi-asserted-by":"publisher","key":"2","DOI":"10.1109\/ICICDT.2007.4299568"},{"doi-asserted-by":"publisher","key":"1","DOI":"10.1109\/JPROC.2006.873612"},{"year":"2010","author":"jones","journal-title":"Technical Viability of Stacked Silicon Interconnect Technology","key":"7"},{"key":"30","article-title":"Automation of DfT Insertion and Interconnect Test Generation for 3D Stacked ICs","author":"deutsch","year":"0","journal-title":"IEEE North-Atlantic Test Workshop (NATW) May 2011"},{"doi-asserted-by":"publisher","key":"6","DOI":"10.1109\/ETS.2011.52"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1109\/ICCAD.2007.4397268"},{"key":"32","first-page":"130","article-title":"8Gb 3D DDR3 DRAM Using Through-Silicon-Via Technology","author":"kang","year":"2009","journal-title":"Proc Int l Solid-States Circuits Conf (ISSCC)"},{"doi-asserted-by":"publisher","key":"4","DOI":"10.1109\/MM.2007.59"},{"doi-asserted-by":"publisher","key":"31","DOI":"10.1109\/MDT.2003.1188257"},{"doi-asserted-by":"publisher","key":"9","DOI":"10.1109\/TEST.2011.6139181"},{"year":"2010","author":"saban","journal-title":"Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity Bandwidth and Power Efficiency","key":"8"},{"doi-asserted-by":"publisher","key":"19","DOI":"10.1109\/TVLSI.2008.2003513"},{"doi-asserted-by":"publisher","key":"17","DOI":"10.1109\/VTS.2010.5469559"},{"doi-asserted-by":"publisher","key":"18","DOI":"10.1109\/ISSM.2007.4446880"},{"doi-asserted-by":"publisher","key":"15","DOI":"10.1109\/3DIC.2009.5306569"},{"doi-asserted-by":"publisher","key":"16","DOI":"10.1109\/ATS.2009.42"},{"doi-asserted-by":"publisher","key":"13","DOI":"10.1109\/ATS.2010.80"},{"key":"14","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-6107-1","author":"zorian","year":"1997","journal-title":"Multi-Chip Module Test Strategies"},{"doi-asserted-by":"publisher","key":"11","DOI":"10.1109\/TEST.2009.5355573"},{"doi-asserted-by":"publisher","key":"12","DOI":"10.1109\/DATE.2010.5457087"},{"doi-asserted-by":"publisher","key":"21","DOI":"10.1109\/TEST.2010.5699218"},{"doi-asserted-by":"publisher","key":"20","DOI":"10.1109\/ETSYM.2010.5512785"},{"key":"49","article-title":"DfT and Test Flows for Stacked Die","author":"racine","year":"0","journal-title":"Digest of IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST) September 2011"},{"doi-asserted-by":"publisher","key":"48","DOI":"10.1109\/ATS.2011.58"},{"doi-asserted-by":"publisher","key":"45","DOI":"10.1109\/VTS.2010.5469556"},{"doi-asserted-by":"publisher","key":"44","DOI":"10.1109\/TCAD.2004.826558"},{"doi-asserted-by":"publisher","key":"47","DOI":"10.1007\/s10836-011-5269-9"},{"doi-asserted-by":"publisher","key":"46","DOI":"10.1109\/3DIC.2010.5751450"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1109\/ATS.2011.36"},{"key":"51","article-title":"WideIO Memories","author":"shoemaker","year":"0","journal-title":"GSA 3D IC Working Group Meeting December 2011"},{"year":"0","author":"adam b","key":"50"}],"event":{"name":"2012 Design, Automation & Test in Europe Conference & Exhibition (DATE 2012)","start":{"date-parts":[[2012,3,12]]},"location":"Dresden","end":{"date-parts":[[2012,3,16]]}},"container-title":["2012 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6171057\/6176405\/06176689.pdf?arnumber=6176689","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T03:48:04Z","timestamp":1498016884000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6176689\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,3]]},"references-count":51,"URL":"https:\/\/doi.org\/10.1109\/date.2012.6176689","relation":{},"subject":[],"published":{"date-parts":[[2012,3]]}}}