{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T19:35:34Z","timestamp":1725564934855},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,3]]},"DOI":"10.1109\/date.2012.6176712","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T13:16:29Z","timestamp":1361279789000},"page":"1507-1512","source":"Crossref","is-referenced-by-count":0,"title":["Modeling and design exploration of FBDRAM as on-chip memory"],"prefix":"10.1109","author":[{"family":"Guangyu Sun","sequence":"first","affiliation":[]},{"family":"Cong Xu","sequence":"additional","affiliation":[]},{"family":"Yuan Xie","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919638"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2003.159781"},{"key":"14","article-title":"Sram parametric failure analysis","author":"wang","year":"2008","journal-title":"DAC"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/4.75050"},{"key":"12","first-page":"128","article-title":"1.2V 1.6Gb\/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I\/O sense amplifier and segmented subarray architecture","author":"moon","year":"2009","journal-title":"ISSCC09"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2008.4588575"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2010.5556212"},{"key":"1","article-title":"A novel low-voltage biasing scheme for double gate FBC achieving 5s retention and 1016 endurance at 85C","author":"lu","year":"2010","journal-title":"IEDM"},{"journal-title":"Timing models for MOS circuits","year":"1983","author":"horowitz","key":"10"},{"key":"7","first-page":"23","article-title":"A new 1t dram cell with enhanced floating body ef","author":"lin","year":"2006","journal-title":"MTDT06"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2011.2134065"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2008.922796"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2007.896883"},{"journal-title":"Process Integration Devices and Structures 2010 Update","year":"0","key":"9"},{"journal-title":"CACTI 5 1 Technical Report","year":"2008","author":"thoziyoor","key":"8"}],"event":{"name":"2012 Design, Automation & Test in Europe Conference & Exhibition (DATE 2012)","start":{"date-parts":[[2012,3,12]]},"location":"Dresden","end":{"date-parts":[[2012,3,16]]}},"container-title":["2012 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6171057\/6176405\/06176712.pdf?arnumber=6176712","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T15:22:14Z","timestamp":1490109734000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6176712\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,3]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/date.2012.6176712","relation":{},"subject":[],"published":{"date-parts":[[2012,3]]}}}