{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,28]],"date-time":"2025-11-28T12:25:23Z","timestamp":1764332723796},"reference-count":32,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,11]]},"DOI":"10.1109\/dcis.2018.8681491","type":"proceedings-article","created":{"date-parts":[[2019,4,27]],"date-time":"2019-04-27T07:14:45Z","timestamp":1556349285000},"page":"1-6","source":"Crossref","is-referenced-by-count":7,"title":["Approximate Wireless Networks-on-Chip"],"prefix":"10.1109","author":[{"given":"Giuseppe","family":"Ascia","sequence":"first","affiliation":[]},{"given":"Vincenzo","family":"Catania","sequence":"additional","affiliation":[]},{"given":"Salvatore","family":"Monteleone","sequence":"additional","affiliation":[]},{"given":"Maurizio","family":"Palesi","sequence":"additional","affiliation":[]},{"given":"Davide","family":"Patti","sequence":"additional","affiliation":[]},{"given":"John","family":"Jose","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref32","article-title":"Parsec 2.0: A new benchmark suite for chip-multiprocessors","author":"bienia","year":"2009","journal-title":"Proceedings of the 5th Annual Workshop on Modeling Benchmarking and Simulation"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1995.524546"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/3138807"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1806799.1806808"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540711"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ESTIMedia.2013.6704499"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2786763.2694351"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1961296.1950390"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.22"},{"key":"ref16","article-title":"Clumsy value cache: An approximate memoization technique for mobile gpu fragment shaders","author":"keramidas","year":"2015","journal-title":"Workshop on Approximate Computing"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2717311"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2414729.2414738"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1993316.1993518"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2010.37"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2287696.2287706"},{"year":"2014","key":"ref27"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.900236"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2017.2777863"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2012.2193835"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2751163"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.917729"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3145812"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3140659.3080241"},{"key":"ref1","article-title":"Exascale computing study: Technology challenges in achieving exascale systems","author":"bergman","year":"2008","journal-title":"Defense Advanced Research Projects Agency Information Processing Techniques Office (DARPA IPTO)"},{"year":"0","key":"ref20","article-title":"NanGate 45nm open cell library"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/HOTI.2011.12"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea5020038"},{"journal-title":"Digital and Analog Communication Systems","year":"2007","author":"couch","key":"ref24"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2010.5540799"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2016.01.019"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2017.8052878"}],"event":{"name":"2018 Conference on Design of Circuits and Integrated Systems (DCIS)","start":{"date-parts":[[2018,11,14]]},"location":"Lyon, France","end":{"date-parts":[[2018,11,16]]}},"container-title":["2018 Conference on Design of Circuits and Integrated Systems (DCIS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8679952\/8681454\/08681491.pdf?arnumber=8681491","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,12,23]],"date-time":"2021-12-23T15:23:01Z","timestamp":1640272981000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8681491\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,11]]},"references-count":32,"URL":"https:\/\/doi.org\/10.1109\/dcis.2018.8681491","relation":{},"subject":[],"published":{"date-parts":[[2018,11]]}}}