{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T17:54:04Z","timestamp":1725731644938},"reference-count":19,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,11]]},"DOI":"10.1109\/dcis201949030.2019.8959892","type":"proceedings-article","created":{"date-parts":[[2020,1,17]],"date-time":"2020-01-17T02:11:20Z","timestamp":1579227080000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Assessing SET Sensitivity of Mixed-Signal Circuits at Early Design Stages"],"prefix":"10.1109","author":[{"given":"Aranzazu","family":"Fernandez-Alvarez","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marta","family":"Portela-Garcia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mario","family":"Garcia-Valderas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Celia","family":"Lopez-Ongil","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Samuel Sordo","family":"Ibanez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Servando Espejo","family":"Meana","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/TNS.2015.2447391"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/TC.2010.262"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/DCIS.2018.8681485"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/DATE.2004.1268909"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/BMAS.2010.6156601"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/DCIS.2016.7845364"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1109\/JESTPE.2017.2739710"},{"year":"0","journal-title":"NGSpice-Mixed Mode-Mixed Level Circuit Simulator","key":"ref17"},{"year":"0","journal-title":"Zynq-7000 All Programmable SoC Technical Reference Manual","key":"ref18"},{"year":"0","journal-title":"Zedboard description","key":"ref19"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/TNS.2015.2456831"},{"year":"2015","journal-title":"Technique for radiation effects mitigation in ASICs and FPGAs handbook","key":"ref3"},{"key":"ref6","article-title":"Chapter 1: ‘Mixed-Signal Design Trends and Challenges,’ in Mixed signal methodology guide","author":"chen","year":"2012","journal-title":"Cadence Design Systems"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/DCIS.2014.7035582"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/RADECS.2011.6131392"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/TNS.2006.889115"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/TNS.2013.2255624"},{"year":"0","journal-title":"NASA\/GSFC Radiation Effects and Analysis","key":"ref1"},{"key":"ref9","first-page":"586","article-title":"SCFIT: A FPGA-based fault injection technique for SEU fault model","author":"mohammadi","year":"2013","journal-title":"2012 Des Autom Test Eur Conf Exhib"}],"event":{"name":"2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS)","start":{"date-parts":[[2019,11,20]]},"location":"Bilbao, Spain","end":{"date-parts":[[2019,11,22]]}},"container-title":["2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8952591\/8959817\/08959892.pdf?arnumber=8959892","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,15]],"date-time":"2022-07-15T03:13:14Z","timestamp":1657854794000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8959892\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,11]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/dcis201949030.2019.8959892","relation":{},"subject":[],"published":{"date-parts":[[2019,11]]}}}