{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T14:57:53Z","timestamp":1730213873346,"version":"3.28.0"},"reference-count":21,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,11,18]],"date-time":"2020-11-18T00:00:00Z","timestamp":1605657600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,11,18]],"date-time":"2020-11-18T00:00:00Z","timestamp":1605657600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,11,18]],"date-time":"2020-11-18T00:00:00Z","timestamp":1605657600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,11,18]]},"DOI":"10.1109\/dcis51330.2020.9268638","type":"proceedings-article","created":{"date-parts":[[2020,11,30]],"date-time":"2020-11-30T21:59:32Z","timestamp":1606773572000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Hardware architecture for integrate-and-fire signal reconstruction on FPGA"],"prefix":"10.1109","author":[{"given":"Guilherme","family":"Carvalho","sequence":"first","affiliation":[]},{"given":"Joao Canas","family":"Ferreira","sequence":"additional","affiliation":[]},{"given":"Vitor Grade","family":"Tavares","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.2009.2037040"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1155\/2010\/469658"},{"key":"ref12","first-page":"-353v","article-title":"Signal reconstruction from spiking neuron models","volume":"5","author":"wei","year":"0","journal-title":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat No 04CH37512)"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2003.1201780"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/NER.2009.5109321"},{"key":"ref15","first-page":"237","article-title":"Fast recovery algorithms of time encoded bandlimited signals","volume":"4","author":"lazar","year":"2005","journal-title":"IEEE International Conference on Acoustics Speech and Signal Processing"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1090\/S0002-9904-1920-03322-7"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1017\/S0305004100030401"},{"key":"ref18","first-page":"410","article-title":"FPGA accelerating three QR decomposition algorithms in the unified pipelined framework","volume":"410073","author":"dou","year":"0"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-03644-6_9"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/s00422-007-0189-6"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICUWB.2014.6959029"},{"key":"ref6","first-page":"1","article-title":"Time Encoding of Bandlimited Signals, an Overview","author":"lazar","year":"2005","journal-title":"Conference on Telecommunication Systems Modeling and Analysis no October"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/S0092-8240(05)80004-7"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1016\/j.acha.2013.02.002"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1016\/j.neucom.2004.01.022"},{"key":"ref2","first-page":"4903","article-title":"An asynchronous delta-sigma converter implementation","author":"wei","year":"2006","journal-title":"2006 IEEE International Symposium on Circuits and Systems"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5938092"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-57081-5"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1137\/0910004"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1161\/01.CIR.101.23.e215"}],"event":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","start":{"date-parts":[[2020,11,18]]},"location":"Segovia, Spain","end":{"date-parts":[[2020,11,20]]}},"container-title":["2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9268497\/9268612\/09268638.pdf?arnumber=9268638","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,27]],"date-time":"2022-06-27T15:58:59Z","timestamp":1656345539000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9268638\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,11,18]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/dcis51330.2020.9268638","relation":{},"subject":[],"published":{"date-parts":[[2020,11,18]]}}}