{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,3]],"date-time":"2025-10-03T13:15:15Z","timestamp":1759497315351},"reference-count":15,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,11,15]],"date-time":"2023-11-15T00:00:00Z","timestamp":1700006400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,11,15]],"date-time":"2023-11-15T00:00:00Z","timestamp":1700006400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,11,15]]},"DOI":"10.1109\/dcis58620.2023.10335963","type":"proceedings-article","created":{"date-parts":[[2023,12,11]],"date-time":"2023-12-11T19:41:15Z","timestamp":1702323675000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["High-Throughput DTW accelerator with minimum area in AMD FPGA by HLS"],"prefix":"10.1109","author":[{"given":"Marco","family":"Hormigo-Jim\u00e9nez","sequence":"first","affiliation":[{"name":"Industrial Engineering School Universidad de Málaga,Málaga,Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Javier","family":"Hormigo","sequence":"additional","affiliation":[{"name":"Universidad de Málaga,Dept. Computer Architecture,Malaga,Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TASSP.1978.1163055"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2729344"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ECS.2014.6892646"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/29.90369"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/GCCE50665.2020.9292068"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IGCC.2015.7393707"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP49362.2020.00015"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/icde.2001.914875"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/s00778-008-0111-4"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.2991\/iske.2007.205"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2339530.2339576"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICDM.2010.21"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2014.10"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TASLP.2022.3180673"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3021066"}],"event":{"name":"2023 38th Conference on Design of Circuits and Integrated Systems (DCIS)","start":{"date-parts":[[2023,11,15]]},"location":"M\u00e1laga, Spain","end":{"date-parts":[[2023,11,17]]}},"container-title":["2023 38th Conference on Design of Circuits and Integrated Systems (DCIS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10335898\/10335962\/10335963.pdf?arnumber=10335963","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,12,19]],"date-time":"2023-12-19T22:26:20Z","timestamp":1703024780000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10335963\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,11,15]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/dcis58620.2023.10335963","relation":{},"subject":[],"published":{"date-parts":[[2023,11,15]]}}}