{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,18]],"date-time":"2025-12-18T14:28:43Z","timestamp":1766068123235,"version":"3.32.0"},"reference-count":15,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,11,13]],"date-time":"2024-11-13T00:00:00Z","timestamp":1731456000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,11,13]],"date-time":"2024-11-13T00:00:00Z","timestamp":1731456000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,11,13]]},"DOI":"10.1109\/dcis62603.2024.10769114","type":"proceedings-article","created":{"date-parts":[[2024,12,3]],"date-time":"2024-12-03T18:54:06Z","timestamp":1733252046000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Smart Carrier for Scan Chain Emulation of ASIC Prototypes under Test"],"prefix":"10.1109","author":[{"given":"Juan Manuel","family":"Gal\u00e1n","sequence":"first","affiliation":[{"name":"CEIT-Basque Research and Technology Alliance (BRTA) Manuel Lardizabal 15,Donostia\/San Sebastián,Spain,20018"}]},{"given":"Ainhoa","family":"Cort\u00e9s","sequence":"additional","affiliation":[{"name":"CEIT-Basque Research and Technology Alliance (BRTA) Manuel Lardizabal 15,Donostia\/San Sebastián,Spain,20018"}]},{"given":"Andoni","family":"Irizar","sequence":"additional","affiliation":[{"name":"CEIT-Basque Research and Technology Alliance (BRTA) Manuel Lardizabal 15,Donostia\/San Sebastián,Spain,20018"}]},{"given":"Alejandro","family":"Arteaga","sequence":"additional","affiliation":[{"name":"University of the Basque Country (UPV\/EHU),Departamento de Tecnología Electrónica,Bilbao,Spain"}]},{"given":"Jos\u00e9 Ignacio","family":"G\u00e1rate","sequence":"additional","affiliation":[{"name":"University of the Basque Country (UPV\/EHU),Departamento de Tecnología Electrónica,Bilbao,Spain"}]},{"given":"Armando","family":"Astarloa","sequence":"additional","affiliation":[{"name":"University of the Basque Country (UPV\/EHU),Departamento de Tecnología Electrónica,Bilbao,Spain"}]}],"member":"263","reference":[{"volume-title":"Digital Design and Computer Architecture, RISC-V Edition - 1st Edition | Elsevier Shop","key":"ref1"},{"key":"ref2","first-page":"14Z","volume-title":"riscvarchive\/riscv-cores-list","volume":"47","year":"2024"},{"volume-title":"PULP Project Information","key":"ref3"},{"volume-title":"Ibex: An embedded 32 bit RISC-V CPU core \u2014 Ibex Documentation 0.1.dev50+g5a8a1a9.d20240217 documentation","key":"ref4"},{"volume-title":"Open source hardware the new reality CV32e40p project | OpenHW group","author":"Schiavone","key":"ref5"},{"volume-title":"The NEORV32 RISCV Processor","year":"2023","author":"Nolting","key":"ref6"},{"volume-title":"SOC4CRIS: Investigaci\u00f3n y Capacitaci\u00f3n del Ecosistema I+D+i en el Dise\u00f1o, Fabricaci\u00f3n y Testing de Semiconductores para Sistemas Cr\u00edticos","year":"2024","key":"ref7"},{"volume-title":"White rabbit official CERN website","key":"ref8"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/LATW.2018.8347236"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IDAACS.2009.5343031"},{"volume-title":"Architecting chiplets for product manufacturing test resiliency","year":"2023","author":"Detofsky","key":"ref11"},{"volume-title":"Zynqberry te0726 by trenz electronics","key":"ref12"},{"volume-title":"Zynq-7000 soc data sheet: Overview (ds190)","year":"2018","key":"ref13"},{"key":"ref14","first-page":"1","article-title":"Ieee standard for test access port and boundary-scan architecture","year":"2013","journal-title":"IEEE Std 1149.1-2013 (Revision of IEEE Std 1149.1-2001)"},{"volume-title":"Amba\u00ae axi and ace protocol specification (h.c)","year":"2021","key":"ref15"}],"event":{"name":"2024 39th Conference on Design of Circuits and Integrated Systems (DCIS)","start":{"date-parts":[[2024,11,13]]},"location":"Catania, Italy","end":{"date-parts":[[2024,11,15]]}},"container-title":["2024 39th Conference on Design of Circuits and Integrated Systems (DCIS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10769040\/10769041\/10769114.pdf?arnumber=10769114","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,10]],"date-time":"2025-01-10T19:56:11Z","timestamp":1736538971000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10769114\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,11,13]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/dcis62603.2024.10769114","relation":{},"subject":[],"published":{"date-parts":[[2024,11,13]]}}}