{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,24]],"date-time":"2025-06-24T06:48:00Z","timestamp":1750747680176,"version":"3.32.0"},"reference-count":51,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,11,13]],"date-time":"2024-11-13T00:00:00Z","timestamp":1731456000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,11,13]],"date-time":"2024-11-13T00:00:00Z","timestamp":1731456000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,11,13]]},"DOI":"10.1109\/dcis62603.2024.10769177","type":"proceedings-article","created":{"date-parts":[[2024,12,3]],"date-time":"2024-12-03T18:54:06Z","timestamp":1733252046000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Hardware coprocessor integration with NEORV32: characterization for efficient implementation of RISC-V-based AI SoCs"],"prefix":"10.1109","author":[{"given":"Unai","family":"Sainz-Estebanez","sequence":"first","affiliation":[{"name":"University of the Basque Country (UPV\/EHU),Grupo de Diseño en Electrónica Digital (GDED),Bilbao,Basque Country,Spain"}]},{"given":"Unai","family":"Martinez-Corral","sequence":"additional","affiliation":[{"name":"University of the Basque Country (UPV\/EHU),Dept. Electronics Technology,Bilbao,Basque Country,Spain"}]},{"given":"Koldo","family":"Basterretxea","sequence":"additional","affiliation":[{"name":"University of the Basque Country (UPV\/EHU),Dept. Electronics Technology,Bilbao,Basque Country,Spain"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2022.3226481"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/COMST.2022.3218527"},{"volume-title":"OpenSPARC","year":"2005","key":"ref3"},{"volume-title":"LEON","year":"1997","key":"ref4"},{"volume-title":"OpenRISC","year":"2000","key":"ref5"},{"volume-title":"OpenCores","year":"1999","key":"ref6"},{"volume-title":"Power ISA","year":"2006","key":"ref7"},{"volume-title":"SuperH","year":"1992","key":"ref8"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2013.7478332"},{"volume-title":"Google","year":"1998","key":"ref10"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS57527.2023.00024"},{"volume-title":"VexRiscv - A FPGA friendly 32 bit RISC-V CPU","year":"2016","author":"Papon","key":"ref12"},{"volume-title":"NEORV32 - A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontrollerlike SoC","year":"2024","author":"Nolting","key":"ref13"},{"volume-title":"Draft Proposed RISC-V Composable Custom Extensions Specification","year":"2019","author":"Gray","key":"ref14"},{"volume-title":"GitHub","year":"2008","key":"ref15"},{"volume-title":"GitLab","year":"2011","key":"ref16"},{"volume-title":"Microwatt - A tiny Open POWER ISA softcore","year":"2019","author":"Blanchard","key":"ref17"},{"volume-title":"Chiselwatt - A tiny POWER Open ISA soft processor","year":"2019","author":"Blanchard","key":"ref18"},{"volume-title":"Rocket Chip","year":"2014","author":"Waterman","key":"ref19"},{"volume-title":"PicoRV32 - A Size-Optimized RISCV CPU","year":"2021","author":"Xenia Wolf","key":"ref20"},{"volume-title":"Hummingbirdv2 E203 Core and SoC","year":"2020","key":"ref21"},{"volume-title":"DarkRISCV","year":"2018","author":"Samsoniuk","key":"ref22"},{"volume-title":"RISC-V CPU (Tape-Out with U18 Technology)","year":"2019","author":"Lin","key":"ref23"},{"volume-title":"RISCV-Atom soft-core processor","year":"2021","author":"Singh","key":"ref24"},{"volume-title":"RISC-V Steel","year":"2024","author":"Calcada","key":"ref25"},{"volume-title":"ORCA RISC-V RV32IM core","year":"2015","author":"Vandergriendt","key":"ref26"},{"volume-title":"The Potato Processor","year":"2015","author":"Klomsten Skordal","key":"ref27"},{"volume-title":"RPU - Basic RISC-V CPU","year":"2020","author":"Riley","key":"ref28"},{"volume-title":"ReonV RISC-V","year":"2018","author":"Castro","key":"ref29"},{"volume-title":"Open-Source RISC-V Architecture IDs","year":"2024","key":"ref30"},{"volume-title":"The NEORV32 RISC-V Processor Datasheet","year":"2020","author":"Nolting","key":"ref31"},{"volume-title":"The NEORV32 RISC-V Processor User Guide","year":"2020","author":"Nolting","key":"ref32"},{"volume-title":"AXI4-Stream","year":"2010","key":"ref33"},{"volume-title":"Wishbone Bus.","year":"2010","key":"ref34"},{"volume-title":"AXI4-Lite","year":"2010","key":"ref35"},{"volume-title":"RapidWright","year":"2018","key":"ref36"},{"volume-title":"Runtime-First FPGA Interchange Routing Contes","year":"2024","key":"ref37"},{"volume-title":"Advanced Micro Devices, Inc","year":"1969","key":"ref38"},{"volume-title":"FPGA Interchange Format","year":"2020","key":"ref39"},{"volume-title":"Siemens","year":"1847","key":"ref40"},{"volume-title":"Open Source VHDL Verification Methodology","year":"2013","author":"Lewis","key":"ref41"},{"volume-title":"Universal VHDL Verification Methodology","year":"2013","author":"Tallaksen","key":"ref42"},{"volume-title":"The 2022 Wilson Research Group Functional Verification Study","year":"2022","key":"ref43"},{"volume-title":"Vivado Design Suite","year":"2012","key":"ref44"},{"volume-title":"Ghdl + yosys + ghdl yosys plugin + nextpnr-xilinx + prjxray container","year":"2024","author":"Sainz-Estebanez","key":"ref45"},{"volume-title":"GHDL - VHDL 2008\/93\/87 simulator","year":"2024","author":"Gingold","key":"ref46"},{"volume-title":"YOSYS - Yosys Open SYnthesis Suite","year":"2020","author":"Xenia Wolf","key":"ref47"},{"volume-title":"Nextpnr-Xilinx - Experimental flows using nextpnr for Xilinx devices","year":"2020","author":"Shah","key":"ref48"},{"volume-title":"Documenting the Xilinx 7-series bitstream format","year":"2020","key":"ref49"},{"volume-title":"Questa advanced simulator","year":"2011","key":"ref50"},{"volume-title":"VUnit - Testing framework for VHDL\/SystemVerilog","year":"2024","author":"Asplund","key":"ref51"}],"event":{"name":"2024 39th Conference on Design of Circuits and Integrated Systems (DCIS)","start":{"date-parts":[[2024,11,13]]},"location":"Catania, Italy","end":{"date-parts":[[2024,11,15]]}},"container-title":["2024 39th Conference on Design of Circuits and Integrated Systems (DCIS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10769040\/10769041\/10769177.pdf?arnumber=10769177","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,10]],"date-time":"2025-01-10T19:56:00Z","timestamp":1736538960000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10769177\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,11,13]]},"references-count":51,"URL":"https:\/\/doi.org\/10.1109\/dcis62603.2024.10769177","relation":{},"subject":[],"published":{"date-parts":[[2024,11,13]]}}}