{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T15:07:16Z","timestamp":1742396836725},"reference-count":6,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007]]},"DOI":"10.1109\/ddecs.2007.4295262","type":"proceedings-article","created":{"date-parts":[[2008,7,18]],"date-time":"2008-07-18T16:49:29Z","timestamp":1216399769000},"page":"1-6","source":"Crossref","is-referenced-by-count":9,"title":["Instruction Memory Architecture Evaluation on Multiprocessor FPGA MPEG-4 Encoder"],"prefix":"10.1109","author":[{"given":"Ari","family":"Kulmala","sequence":"first","affiliation":[]},{"given":"Erno","family":"Salminen","sequence":"additional","affiliation":[]},{"given":"Timo D.","family":"Hamalainen","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"crossref","DOI":"10.1186\/1687-3963-2006-038494","article-title":"Scalable MPEG-4 Encoder on FPGA Multiprocessor SoC","author":"kulmala","year":"2006","journal-title":"EURASIP Journal on Embedded Systems"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2006.1649571"},{"journal-title":"version SII5Vl-1 1","article-title":"Stratix II Device Handbook, Volume 1","year":"2004","key":"ref6"},{"journal-title":"Section 5 version NII5VI-6 1","article-title":"NiosII Processor Reference Handbook","year":"2006","key":"ref5"},{"journal-title":"Computer Architecture - A Quantitative Approach","year":"2003","author":"hennessy","key":"ref2"},{"key":"ref1","first-page":"15","article-title":"Performance optimization of an FPGA-based configurable multiprocessor for matrix operations","author":"wang","year":"2003","journal-title":"Proc Field-Program Technol (FPT)"}],"event":{"name":"2007 IEEE Design and Diagnostics of Electronic Circuits and Systems","start":{"date-parts":[[2007,4,11]]},"location":"Krakow, Poland","end":{"date-parts":[[2007,4,13]]}},"container-title":["2007 IEEE Design and Diagnostics of Electronic Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4295238\/4295239\/04295262.pdf?arnumber=4295262","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T10:04:53Z","timestamp":1497780293000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4295262\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/ddecs.2007.4295262","relation":{},"subject":[],"published":{"date-parts":[[2007]]}}}