{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T15:41:00Z","timestamp":1725464460732},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007]]},"DOI":"10.1109\/ddecs.2007.4295276","type":"proceedings-article","created":{"date-parts":[[2008,7,18]],"date-time":"2008-07-18T12:49:29Z","timestamp":1216385369000},"page":"1-6","source":"Crossref","is-referenced-by-count":8,"title":["March CRF: an Efficient Test for Complex Read Faults in SRAM Memories"],"prefix":"10.1109","author":[{"given":"Luigi","family":"Dilillo","sequence":"first","affiliation":[]},{"given":"Bashir M.","family":"Al-Hashimi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/4.859510"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"292","DOI":"10.1109\/VTS.2005.58","article-title":"Modeling and testing of SRAM for new failure mechanisms due to process variations in nanoscale CMOS","author":"qikai","year":"2005","journal-title":"Proc VLSI Test Symposium"},{"key":"ref12","article-title":"Fundamentals of Modern VLSI Devices","author":"taur","year":"1998","journal-title":"Cambridge University Press"},{"journal-title":"Berkeley predictive technology model","year":"2005","key":"ref13"},{"key":"ref14","first-page":"165","article-title":"Accurate stacking effect macro-modeling of leakage power in sub-100 nm circuits","author":"yang","year":"2005","journal-title":"Proc International Conference on VLSI Design"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.859476"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2004.1299236"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2001.915069"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065804"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775920"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/4.918909"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852295"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966731"},{"year":"2003","key":"ref1","article-title":"International Technology Roadmap for Semiconductors (ITRS)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2005.33"}],"event":{"name":"2007 IEEE Design and Diagnostics of Electronic Circuits and Systems","start":{"date-parts":[[2007,4,11]]},"location":"Krakow, Poland","end":{"date-parts":[[2007,4,13]]}},"container-title":["2007 IEEE Design and Diagnostics of Electronic Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4295238\/4295239\/04295276.pdf?arnumber=4295276","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,12]],"date-time":"2019-05-12T15:35:06Z","timestamp":1557675306000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4295276\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/ddecs.2007.4295276","relation":{},"subject":[],"published":{"date-parts":[[2007]]}}}