{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T14:55:43Z","timestamp":1730213743104,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007]]},"DOI":"10.1109\/ddecs.2007.4295308","type":"proceedings-article","created":{"date-parts":[[2008,7,18]],"date-time":"2008-07-18T12:49:29Z","timestamp":1216385369000},"page":"1-4","source":"Crossref","is-referenced-by-count":1,"title":["Reticle Exposure Plans for Multi-Project Wafers"],"prefix":"10.1109","author":[{"given":"Rung-Bin","family":"Lin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Da-Wei","family":"Hsu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ming-Hsine","family":"Kuo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Meng-Chiou","family":"Wu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"610","article-title":"Reticle floorplanning and wafer dicing for multiple project wafers","author":"wu","year":"2005","journal-title":"ISQED"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VDAT.2006.258145"},{"key":"ref12","first-page":"314","article-title":"A comparative study on dicing of multiple project wafers","author":"wu","year":"2005","journal-title":"ISVLSI"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1118299.1118479"},{"key":"ref14","first-page":"142","article-title":"Cost effective strategies for ASIC masks","volume":"5043","author":"pramanik","year":"2003","journal-title":"SPIE"},{"journal-title":"International SEMATECH","article-title":"Optical lithography cost of ownership (COO) – Final Report for LITG501","year":"0","key":"ref15"},{"key":"ref4","article-title":"Pattern forming system","author":"nakamura","year":"1994","journal-title":"US Patent"},{"key":"ref3","article-title":"Technique for optimizing the number of IC chips obtainable from a wafer","author":"lucas","year":"1997","journal-title":"US Patent"},{"year":"0","key":"ref6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1117\/12.59818"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/66.920727"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/66.778206"},{"key":"ref2","article-title":"Method for optimizing the integrated circuit chip size for efficient manufacturing","volume":"b1","author":"vickery","year":"2003","journal-title":"US Patent"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MSE.2001.932391"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1117\/12.632036"}],"event":{"name":"2007 IEEE Design and Diagnostics of Electronic Circuits and Systems","start":{"date-parts":[[2007,4,11]]},"location":"Krakow, Poland","end":{"date-parts":[[2007,4,13]]}},"container-title":["2007 IEEE Design and Diagnostics of Electronic Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4295238\/4295239\/04295308.pdf?arnumber=4295308","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,15]],"date-time":"2017-03-15T20:31:34Z","timestamp":1489609894000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4295308\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/ddecs.2007.4295308","relation":{},"subject":[],"published":{"date-parts":[[2007]]}}}