{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T15:56:48Z","timestamp":1761580608626,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,4]]},"DOI":"10.1109\/ddecs.2008.4538763","type":"proceedings-article","created":{"date-parts":[[2008,6,10]],"date-time":"2008-06-10T15:58:11Z","timestamp":1213113491000},"page":"1-6","source":"Crossref","is-referenced-by-count":31,"title":["Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip"],"prefix":"10.1109","author":[{"given":"Zhonghai","family":"Lu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lei","family":"Xia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Axel","family":"Jantsch","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2003.1231923"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1269002"},{"journal-title":"Data structures algorithms and applications in C","year":"2004","author":"sahni","key":"12"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1006\/jcom.1996.0035"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/1132952.1132953"},{"journal-title":"Local Search in Combinatorial Optimization","year":"1997","key":"1"},{"key":"10","article-title":"slot allocation using logical networks for tdm virtual circuit configuration for network-on-chip","author":"lu","year":"2007","journal-title":"Proceedings of the International Conference on Computer-Aided Design (ICCAD '07)"},{"key":"7","doi-asserted-by":"crossref","first-page":"671","DOI":"10.1126\/science.220.4598.671","article-title":"optimization by simulated annealing","volume":"220","author":"kirkpatrick","year":"1983","journal-title":"Science"},{"key":"6","article-title":"exploiting the routing flexibility for energy\/performance aware mapping of regular noc architectures","author":"hu","year":"2003","journal-title":"Proc Design Automation and Test in Europe"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/1084834.1084857"},{"journal-title":"Computers and Intractability A Guide to the Theory of NP-Completeness","year":"1979","author":"garey","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1007\/BF01379319"},{"key":"8","first-page":"406","article-title":"an efficient algorithm for the physical mapping of clustered taskgraphs onto multiprocessor architectures","author":"koziris","year":"2000","journal-title":"Proc Euromicro Workshop Parallel and Distributed Processing"}],"event":{"name":"2008 11th International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","start":{"date-parts":[[2008,4,16]]},"location":"Bratislava, Slovakia","end":{"date-parts":[[2008,4,18]]}},"container-title":["2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4534845\/4538735\/04538763.pdf?arnumber=4538763","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T04:59:41Z","timestamp":1497761981000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4538763\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,4]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/ddecs.2008.4538763","relation":{},"subject":[],"published":{"date-parts":[[2008,4]]}}}