{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T22:35:32Z","timestamp":1729636532936,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009]]},"DOI":"10.1109\/ddecs.2009.5012135","type":"proceedings-article","created":{"date-parts":[[2009,6,2]],"date-time":"2009-06-02T20:44:32Z","timestamp":1243975472000},"page":"230-233","source":"Crossref","is-referenced-by-count":7,"title":["Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memories"],"prefix":"10.1109","author":[{"given":"Grzegorz","family":"Borowik","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tadeusz","family":"Luba","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bogdan J.","family":"Falkowski","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2007.4295261"},{"key":"2","first-page":"28","article-title":"improved state encoding for fsm implementation in fpga structures with embedded memory blocks","volume":"54","author":"borowik","year":"2008","journal-title":"Electronics and Telecommunications Quarterly"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2005.1515696"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2004.41"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/329166.329183"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2004.50"},{"key":"5","first-page":"377","article-title":"decomposition of boolean functions specified by cubes","volume":"9","author":"brzozowski","year":"2003","journal-title":"Journal of Multi-Valued Logic & Soft Computing"},{"journal-title":"Logic Minimization Algorithms for VLSI Synthesis","year":"1985","author":"brayton","key":"4"},{"key":"9","first-page":"214","article-title":"a variable wordwidth content addressable memory for fast string matching","author":"nilsen","year":"2004","journal-title":"NorChip"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/TNET.2006.872576"},{"key":"11","doi-asserted-by":"crossref","first-page":"69","DOI":"10.1109\/DSD.2007.4341452","article-title":"an implementation of an address generator using hash memories","author":"sasao","year":"2007","journal-title":"10th Euromicro Conference on Digital System Design Architectures Methods and Tools"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2005.1515804"}],"event":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","start":{"date-parts":[[2009,4,15]]},"location":"Liberec, Czech Republic","end":{"date-parts":[[2009,4,17]]}},"container-title":["2009 12th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4957849\/5012077\/05012135.pdf?arnumber=5012135","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,5,19]],"date-time":"2020-05-19T02:19:59Z","timestamp":1589854799000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5012135\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/ddecs.2009.5012135","relation":{},"subject":[],"published":{"date-parts":[[2009]]}}}