{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:49:48Z","timestamp":1759146588823,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","license":[{"start":{"date-parts":[[2009,4,1]],"date-time":"2009-04-01T00:00:00Z","timestamp":1238544000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2009,4,1]],"date-time":"2009-04-01T00:00:00Z","timestamp":1238544000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,4]]},"DOI":"10.1109\/ddecs.2009.5012141","type":"proceedings-article","created":{"date-parts":[[2009,6,2]],"date-time":"2009-06-02T20:44:32Z","timestamp":1243975472000},"page":"258-263","source":"Crossref","is-referenced-by-count":9,"title":["An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs"],"prefix":"10.1109","author":[{"given":"L.","family":"Ciganda","sequence":"first","affiliation":[{"name":"Universidad de la Republica Uruguay, Montevideo, Uruguay"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"F.","family":"Abate","sequence":"additional","affiliation":[{"name":"Politecnico di Torino, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"Bernardi","sequence":"additional","affiliation":[{"name":"Politecnico di Torino, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Bruno","sequence":"additional","affiliation":[{"name":"Politecnico di Torino, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Sonza Reorda","sequence":"additional","affiliation":[{"name":"Politecnico di Torino, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.811451"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/43.913754"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2006.105"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2003.822703"},{"journal-title":"Virtex II Pro Platform FPGAs Complete Datasheet","year":"0","key":"7"},{"key":"6","first-page":"194","author":"bernardi","year":"2008","journal-title":"A Novel Methodology for Reducing Soc Test Data Volume on Fpga-Based Testers"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1186\/1471-2105-9-11"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2006.229214"},{"key":"9","first-page":"449","article-title":"the enhanced suffix array and its application to genome analysis","author":"abouelhoda","year":"2002","journal-title":"WABI"},{"journal-title":"XUP Virtex II Pro Development System HW Reference Manual","year":"0","key":"8"}],"event":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","start":{"date-parts":[[2009,4,15]]},"location":"Liberec, Czech Republic","end":{"date-parts":[[2009,4,17]]}},"container-title":["2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4957849\/5012077\/05012141.pdf?arnumber=5012141","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T17:45:53Z","timestamp":1729705553000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/5012141\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,4]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/ddecs.2009.5012141","relation":{},"subject":[],"published":{"date-parts":[[2009,4]]}}}