{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T14:57:02Z","timestamp":1730213822623,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,4]]},"DOI":"10.1109\/ddecs.2011.5783063","type":"proceedings-article","created":{"date-parts":[[2011,6,7]],"date-time":"2011-06-07T13:09:21Z","timestamp":1307452161000},"page":"131-134","source":"Crossref","is-referenced-by-count":4,"title":["A 5Gb\/s equalizer for USB 3.0 receiver in 65 nm CMOS technology"],"prefix":"10.1109","author":[{"given":"Jakub","family":"Kopanski","sequence":"first","affiliation":[]},{"given":"Witold A.","family":"Pleskacz","sequence":"additional","affiliation":[]},{"given":"Dariusz","family":"Pienkowski","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"year":"2009","key":"ref4"},{"journal-title":"S-parameter tables for the superspeed channel S-parameter models in Touchstone format","year":"0","key":"ref3"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.903076"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.857354"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.822774"},{"key":"ref5","article-title":"Physical layer (PHY) specification","author":"heck","year":"2010","journal-title":"Super-Speed USB Developers Conference"},{"journal-title":"White Paper USB Implementers Forum","article-title":"USB 3.0 CDR model","year":"2009","key":"ref12"},{"key":"ref8","article-title":"A S-Gb\/s continuous-time adaptive equalizer and CDR using 0.18 ?m cmos","volume":"2","author":"kim","year":"2008"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005535"},{"journal-title":"Universal Serial Bus Specification 3 0","year":"2008","key":"ref2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.845563"},{"journal-title":"CMOS Circuit Design Layout and Simulation","year":"0","author":"baker","key":"ref1"}],"event":{"name":"Systems (DDECS)","start":{"date-parts":[[2011,4,13]]},"location":"Cottbus, Germany","end":{"date-parts":[[2011,4,15]]}},"container-title":["14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5771301\/5783023\/05783063.pdf?arnumber=5783063","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T02:38:50Z","timestamp":1490063930000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5783063\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,4]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/ddecs.2011.5783063","relation":{},"subject":[],"published":{"date-parts":[[2011,4]]}}}