{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T00:40:00Z","timestamp":1725410400855},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,4]]},"DOI":"10.1109\/ddecs.2011.5783111","type":"proceedings-article","created":{"date-parts":[[2011,6,7]],"date-time":"2011-06-07T13:09:21Z","timestamp":1307452161000},"page":"359-364","source":"Crossref","is-referenced-by-count":0,"title":["On using a SPICE-like TSTAC™ eFlash model for design and test"],"prefix":"10.1109","author":[{"given":"P.-D.","family":"Mauroux","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Virazel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Bosio","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L.","family":"Dilillo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"Girard","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Pravossoudovitch","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"B.","family":"Godard","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.","family":"Festes","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L.","family":"Vachez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"article-title":"Semiconductor Memories: Technology, Testing and Reliability","year":"1997","author":"sharma","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/5.622505"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2006.19"},{"key":"ref10","first-page":"128","article-title":"A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme","author":"suh","year":"1995","journal-title":"Solid-State Circuits Conference"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.816546"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1063\/1.1657043"},{"key":"ref8","first-page":"81","article-title":"A Two-Layer SPICE Model of the ATMEL TSTAC™ eFlash Memory Technology for Defect Injection and Faulty Behavior Prediction","author":"mauroux","year":"2010","journal-title":"Proc IEEE Eur Test Symp"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-008-5096-9"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/5.220908"},{"journal-title":"Semiconductor Industry Association (SIA)","article-title":"International Technology Roadmap for Semiconductors (ITRS)","year":"2008","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1063\/1.3293291"}],"event":{"name":"Systems (DDECS)","start":{"date-parts":[[2011,4,13]]},"location":"Cottbus, Germany","end":{"date-parts":[[2011,4,15]]}},"container-title":["14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5771301\/5783023\/05783111.pdf?arnumber=5783111","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T04:52:00Z","timestamp":1490071920000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5783111\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,4]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/ddecs.2011.5783111","relation":{},"subject":[],"published":{"date-parts":[[2011,4]]}}}