{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,22]],"date-time":"2025-05-22T04:08:11Z","timestamp":1747886891359,"version":"3.41.0"},"reference-count":16,"publisher":"IEEE","license":[{"start":{"date-parts":[[2012,4,1]],"date-time":"2012-04-01T00:00:00Z","timestamp":1333238400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2012,4,1]],"date-time":"2012-04-01T00:00:00Z","timestamp":1333238400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,4]]},"DOI":"10.1109\/ddecs.2012.6219032","type":"proceedings-article","created":{"date-parts":[[2012,6,22]],"date-time":"2012-06-22T23:29:31Z","timestamp":1340407771000},"page":"95-100","source":"Crossref","is-referenced-by-count":1,"title":["Low-area boundary BIST architecture for mesh-like network-on-chip"],"prefix":"10.1109","author":[{"given":"Jaan","family":"Raik","sequence":"first","affiliation":[{"name":"Tallinn University of Technology, Estonia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vineeth","family":"Govind","sequence":"additional","affiliation":[{"name":"Tallinn University of Technology, Estonia"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","first-page":"684","article-title":"Route packets, not wires: On-chip interconnection networks","volume-title":"Proc. of the Design Automation Conference","author":"Dally","year":"2001"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379045"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2002.1016885"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998309"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MCOM.2003.1232240"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/0-306-48727-6_7"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/54.980050"},{"key":"ref8","article-title":"A Scalable Test Strategie for Network-on-Chip Routers","volume-title":"Proc. of ITC","author":"Amory","year":"2005"},{"key":"ref9","article-title":"Towards an Almost C-Testable NoC Test Strategy","volume-title":"IEEE East-West Design and Test Symposium","author":"Peters\u00e9n","year":"2007"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/vts.2007.26"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2006.260967"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2008.0096"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763109"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1269001"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008335130158"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1988.207851"}],"event":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","start":{"date-parts":[[2012,4,18]]},"location":"Tallinn, Estonia","end":{"date-parts":[[2012,4,20]]}},"container-title":["2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6213418\/6219000\/06219032.pdf?arnumber=6219032","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T05:56:05Z","timestamp":1747806965000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6219032\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,4]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/ddecs.2012.6219032","relation":{},"subject":[],"published":{"date-parts":[[2012,4]]}}}