{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T20:19:05Z","timestamp":1725653945852},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,4]]},"DOI":"10.1109\/ddecs.2012.6219040","type":"proceedings-article","created":{"date-parts":[[2012,6,22]],"date-time":"2012-06-22T23:29:31Z","timestamp":1340407771000},"page":"139-144","source":"Crossref","is-referenced-by-count":4,"title":["System side-channel leakage emulation for HW\/SW security coverification of MPSoCs"],"prefix":"10.1109","author":[{"given":"Armin","family":"Krieg","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Johannes","family":"Grinschgl","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christian","family":"Steger","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Reinhold","family":"Weiss","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Holger","family":"Bock","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Josef","family":"Haid","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"AES128","year":"2012","author":"satyanarayana","key":"19"},{"journal-title":"Leon3 Processor","year":"2010","key":"17"},{"journal-title":"Implementations of AES (Rjindael) in C\/C++ and Assembler","year":"2010","author":"gladman","key":"18"},{"key":"15","first-page":"90","article-title":"Early feedback on side-channel risks with accelerated toggle-counting","author":"chen","year":"2009","journal-title":"Host"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2011.5955001"},{"key":"13","first-page":"205","article-title":"A design flow and evaluation framework for DPA-resistant instruction set extensions","author":"regazzoni","year":"2009","journal-title":"CHES 2009"},{"key":"14","article-title":"Side channel leakage profiling in software","author":"shumov","year":"2010","journal-title":"COSADE"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2006.110"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2007.70234"},{"journal-title":"Power Analysis Attacks Revealing the Secrets of Smart Cards","year":"2007","author":"mangard","key":"3"},{"key":"2","doi-asserted-by":"crossref","first-page":"513","DOI":"10.1007\/BFb0052259","article-title":"Differential fault analysis of secret key cryptosystems","author":"biham","year":"1997","journal-title":"Advances in Cryptology ? CRYPTO 97"},{"journal-title":"Differential power analysis","year":"1999","author":"kocher","key":"1"},{"key":"10","doi-asserted-by":"crossref","first-page":"85","DOI":"10.1007\/0-387-24098-5_7","article-title":"Virtual analysis and reduction of side-channel vulnerabilities of smartcards","author":"den hartog","year":"2005","journal-title":"Formal Aspects in Security and Trust"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1049\/iet-ifs:20060112"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065640"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/4.126534"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2011.5993849"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2011.5955002"},{"key":"8","first-page":"443","article-title":"A unified framework for the analysis of side-channel key recovery attacks","author":"standaert","year":"2009","journal-title":"Advances in Cryptology-Eurocrypt"}],"event":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","start":{"date-parts":[[2012,4,18]]},"location":"Tallinn, Estonia","end":{"date-parts":[[2012,4,20]]}},"container-title":["2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems (DDECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6213418\/6219000\/06219040.pdf?arnumber=6219040","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T20:27:56Z","timestamp":1497990476000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6219040\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,4]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/ddecs.2012.6219040","relation":{},"subject":[],"published":{"date-parts":[[2012,4]]}}}