{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,22]],"date-time":"2025-05-22T04:07:27Z","timestamp":1747886847579,"version":"3.41.0"},"reference-count":4,"publisher":"IEEE","license":[{"start":{"date-parts":[[2012,4,1]],"date-time":"2012-04-01T00:00:00Z","timestamp":1333238400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2012,4,1]],"date-time":"2012-04-01T00:00:00Z","timestamp":1333238400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,4]]},"DOI":"10.1109\/ddecs.2012.6219061","type":"proceedings-article","created":{"date-parts":[[2012,6,22]],"date-time":"2012-06-22T23:29:31Z","timestamp":1340407771000},"page":"219-223","source":"Crossref","is-referenced-by-count":1,"title":["Generation of non-overlapping clock signals without using a feedback loop"],"prefix":"10.1109","author":[{"given":"R.","family":"Spilka","sequence":"first","affiliation":[{"name":"Johannes Kepler University, Institute for Integrated Circuits, 4040 Linz, Austria"}]},{"given":"G.","family":"Hilber","sequence":"additional","affiliation":[{"name":"Johannes Kepler University, Institute for Integrated Circuits, 4040 Linz, Austria"}]},{"given":"A.","family":"Rauchenecker","sequence":"additional","affiliation":[{"name":"Johannes Kepler University, Institute for Integrated Circuits, 4040 Linz, Austria"}]},{"given":"D.","family":"Gruber","sequence":"additional","affiliation":[{"name":"Johannes Kepler University, Institute for Integrated Circuits, 4040 Linz, Austria"}]},{"given":"M.","family":"Sams","sequence":"additional","affiliation":[{"name":"Johannes Kepler University, Institute for Integrated Circuits, 4040 Linz, Austria"}]},{"given":"T.","family":"Ostermann","sequence":"additional","affiliation":[{"name":"Johannes Kepler University, Institute for Integrated Circuits, 4040 Linz, Austria"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-90-481-8652-5"},{"volume-title":"Systematic Design for Optimisation of Pipelined ADCs","author":"Goes","key":"ref2"},{"key":"ref3","first-page":"586","article-title":"A Switching Scheme for switched-capacitor Filters, Which reduces Effect of Parasitic Capacitances Assosiated with Control Terminals, Proc","volume-title":"IEEE International Symposium on Circuits and Systems","volume":"2","author":"Haigh","year":"1983"},{"volume-title":"Principles of CMOS VLSI Design, A System Perspective","year":"1993","author":"Weste","key":"ref4"}],"event":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","start":{"date-parts":[[2012,4,18]]},"location":"Tallinn, Estonia","end":{"date-parts":[[2012,4,20]]}},"container-title":["2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems (DDECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6213418\/6219000\/06219061.pdf?arnumber=6219061","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T05:12:42Z","timestamp":1747804362000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6219061\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,4]]},"references-count":4,"URL":"https:\/\/doi.org\/10.1109\/ddecs.2012.6219061","relation":{},"subject":[],"published":{"date-parts":[[2012,4]]}}}