{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T05:40:25Z","timestamp":1773207625500,"version":"3.50.1"},"reference-count":25,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,4]]},"DOI":"10.1109\/ddecs.2012.6219083","type":"proceedings-article","created":{"date-parts":[[2012,6,22]],"date-time":"2012-06-22T19:29:31Z","timestamp":1340393371000},"page":"330-335","source":"Crossref","is-referenced-by-count":2,"title":["On the use of assertions for embedded-software dynamic verification"],"prefix":"10.1109","author":[{"given":"Giuseppe","family":"Di Guglielmo","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luigi","family":"Di Guglielmo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Franco","family":"Fummi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Graziano","family":"Pravadelli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","year":"2009","journal-title":"IEEE Standard for System Verilog-Unified Hardware Design Specification and Verification Language (IEEE Std 1800-2009)"},{"key":"17","year":"0","journal-title":"Unity-compact Test Framework for C"},{"key":"18","article-title":"Introducing the new accellera open verification library standard","author":"foster","year":"2006","journal-title":"Proc Design Verification Conf"},{"key":"15","author":"heimdahl","year":"2004","journal-title":"Specification Test Coverage Adequacy Criteria= Specification Test Generation Inadequacy Criteria?"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/ICDSN.2000.857510"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2010.5496660"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1201\/b16592"},{"key":"11","year":"0","journal-title":"Zazz"},{"key":"12","year":"0","journal-title":"radCHECK"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/ITICT.2005.1609620"},{"key":"20","doi-asserted-by":"crossref","DOI":"10.1007\/10722167_40","article-title":"Focs automatic generation of simulation checkers from formal specifications","author":"abarbanel","year":"2000","journal-title":"Computer Aided Verification"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.243776"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2005.32"},{"key":"24","author":"pressman","year":"1982","journal-title":"Software Engineering A Practitioner's Approach"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1145\/1297666.1297670"},{"key":"3","author":"deutsch","year":"2003","journal-title":"Static Verification Of Dynamic Properties"},{"key":"2","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-540-24730-2_15","article-title":"A tool for checking ansi-c programs","author":"clarke","year":"2004","journal-title":"Tools and Algorithms for the Construction and Analysis of Systems"},{"key":"10","year":"0","journal-title":"Iassertspec Agnisys"},{"key":"1","author":"foster","year":"2004","journal-title":"Assertion-Based Design"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4020-8586-4"},{"key":"6","year":"2010","journal-title":"IEEE Standard for Property Specification Language (PSL) (IEEE Std 1850-2010)"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TSE.2010.68"},{"key":"4","year":"2007","journal-title":"Overview of GrammaTech Static Analysis Technology"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2010.5647654"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2006.319989"}],"event":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","location":"Tallinn, Estonia","start":{"date-parts":[[2012,4,18]]},"end":{"date-parts":[[2012,4,20]]}},"container-title":["2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems (DDECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6213418\/6219000\/06219083.pdf?arnumber=6219083","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T16:27:57Z","timestamp":1497976077000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6219083\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,4]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/ddecs.2012.6219083","relation":{},"subject":[],"published":{"date-parts":[[2012,4]]}}}