{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T01:20:48Z","timestamp":1729646448433,"version":"3.28.0"},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,4]]},"DOI":"10.1109\/ddecs.2013.6549784","type":"proceedings-article","created":{"date-parts":[[2013,7,9]],"date-time":"2013-07-09T15:43:11Z","timestamp":1373384591000},"page":"30-35","source":"Crossref","is-referenced-by-count":1,"title":["Area-speed efficient modular architecture for GF(2<sup>m<\/sup>) multipliers dedicated for cryptographic applications"],"prefix":"10.1109","author":[{"given":"D.","family":"Pamula","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.","family":"Hrynkiewicz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","first-page":"43","article-title":"Multiplication in GF(2m): Area and time dependency\/efficiency\/complexity analysis","author":"pamula","year":"2010","journal-title":"Proceedings of 10th International IFAC Workshop on Programmable Devices and Embedded Systems (PDES)"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2016753"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.239"},{"journal-title":"Arithmetic Operators on GF(2m) for Cryptographic Applications Performance-power Consumption-security Tradeoffs","year":"2012","author":"pamula","key":"18"},{"key":"15","doi-asserted-by":"crossref","first-page":"89","DOI":"10.1109\/ISCAS.2012.6272184","article-title":"Low-latency area-delay-efficient systolic multiplier over GF(2m) for a wider class of trinomials using parallel register sharing","author":"xie","year":"2012","journal-title":"IEEE International Symposium on Circuits and Systems (ISCAS)"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2185257"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1121040"},{"key":"14","doi-asserted-by":"crossref","first-page":"149","DOI":"10.1023\/A:1008013818413","article-title":"Low-energy digit-serial\/parallel finite field multipliers","volume":"19","author":"song","year":"1998","journal-title":"Journal of VLSI Signal Processing-Systems for Signal Image and Video Technology"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2010.0021"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-69499-1_9"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.147"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9781139172769"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2181434"},{"journal-title":"Fips Pub 186-3 Federal Information Processing Standards Publication Digital Signature Standard (Dss)","year":"2009","author":"gallagher","key":"2"},{"journal-title":"Guide to Elliptic Curve Cryptography","year":"2004","author":"hankerson","key":"1"},{"key":"10","first-page":"37","article-title":"A low-power bit-serial multiplier for finite fields GF(2m)","volume":"4","author":"grossschadl","year":"2001","journal-title":"IEEE International Symposium on Circuits and Systems (ISCAS)"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.67"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2004.47"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1007\/s10440-006-9047-0"},{"key":"4","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4613-1983-2","author":"mceliece","year":"1987","journal-title":"Finite field for scientists and engineers"},{"key":"9","first-page":"300","article-title":"A new bit-serial architecture for field multiplication using polynomial bases","author":"reyhani-masoleh","year":"2008","journal-title":"CHES 2008 LNCS 5154 Springer"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2162594"}],"event":{"name":"2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","start":{"date-parts":[[2013,4,8]]},"location":"Karlovy Vary","end":{"date-parts":[[2013,4,10]]}},"container-title":["2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6533795\/6549768\/06549784.pdf?arnumber=6549784","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,5,14]],"date-time":"2024-05-14T05:14:04Z","timestamp":1715663644000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6549784\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,4]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/ddecs.2013.6549784","relation":{},"subject":[],"published":{"date-parts":[[2013,4]]}}}