{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T07:36:55Z","timestamp":1729669015392,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,4]]},"DOI":"10.1109\/ddecs.2014.6868760","type":"proceedings-article","created":{"date-parts":[[2014,8,8]],"date-time":"2014-08-08T18:34:40Z","timestamp":1407522880000},"page":"39-44","source":"Crossref","is-referenced-by-count":4,"title":["Quality assurance in memory built-in self-test tools"],"prefix":"10.1109","author":[{"given":"Albert","family":"Au","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Artur","family":"Pogiel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Janusz","family":"Rajski","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Piotr","family":"Sydow","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jerzy","family":"Tyszer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Justyna","family":"Zawada","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2002.1181693"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2004.1299235"},{"journal-title":"release 2013 1 Mentor Graphics Corp","article-title":"Tessent® MemoryBIST Usage Guide and Reference","year":"0","key":"ref10"},{"journal-title":"Testing Semiconductor Memories Theory and Practice","year":"1998","author":"van de goor","key":"ref6"},{"journal-title":"Advanced Test Methods for SRAMsEffective Solutions for Dynamic Fault Detection in Nanoscaled Technologies","year":"2010","author":"bosio","key":"ref5"},{"key":"ref8","first-page":"291","article-title":"Simulation-based test algorithm generation for random access memories","author":"wu","year":"2000","journal-title":"Proc VTS"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"480","DOI":"10.1109\/43.992771","article-title":"Fault simulation and test algorithm generation for random access memories","volume":"21","author":"wu","year":"2002","journal-title":"IEEE Trans CAD"},{"key":"ref2","first-page":"19","article-title":"Application of defect injection flow for fault validation in memories","author":"amirkhanyan","year":"2012","journal-title":"Proc EWDTS"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2007.27"},{"journal-title":"High Performance Memory Testing Design Principles Fault Modeling and Self-Test","year":"2003","author":"adams","key":"ref1"}],"event":{"name":"2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","start":{"date-parts":[[2014,4,23]]},"location":"Warsaw, Poland","end":{"date-parts":[[2014,4,25]]}},"container-title":["17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6862738\/6868744\/06868760.pdf?arnumber=6868760","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T18:10:21Z","timestamp":1498155021000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6868760\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,4]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/ddecs.2014.6868760","relation":{},"subject":[],"published":{"date-parts":[[2014,4]]}}}