{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,14]],"date-time":"2024-08-14T06:32:45Z","timestamp":1723617165986},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,4]]},"DOI":"10.1109\/ddecs.2016.7482453","type":"proceedings-article","created":{"date-parts":[[2016,6,2]],"date-time":"2016-06-02T17:06:31Z","timestamp":1464887191000},"source":"Crossref","is-referenced-by-count":2,"title":["A hybrid power modeling approach to enhance high-level power models"],"prefix":"10.1109","author":[{"given":"Alejandro","family":"Nocua","sequence":"first","affiliation":[]},{"given":"Arnaud","family":"Virazel","sequence":"additional","affiliation":[]},{"given":"Alberto","family":"Bosio","sequence":"additional","affiliation":[]},{"given":"Patrick","family":"Girard","sequence":"additional","affiliation":[]},{"given":"Cyril","family":"Chevalier","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"A leakage power estimation method for standard cell based design","author":"zhao","year":"2005","journal-title":"IEEE Conf Electron Devices Solid-State Circuits"},{"key":"ref11","doi-asserted-by":"crossref","DOI":"10.1109\/JPROC.2009.2034476","article-title":"FDSOI Process Technology for Ultralow-Power Electronics","author":"vitale","year":"2010","journal-title":"Proceedings of the IEEE"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1088\/1674-4926\/35\/2\/025005"},{"key":"ref13","article-title":"Cadence","year":"2014","journal-title":"Cadence Spectre Circuit Simulator"},{"key":"ref14","article-title":"Synopsys","year":"2014","journal-title":"Primetime px Signoff power analysis"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/j.jksuci.2014.03.005"},{"key":"ref3","article-title":"Reusable platform design methodology for soc integration and verification","year":"2008","journal-title":"International SoC Design Conference"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.358083"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/92.645074"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2169686"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/370155.370528"},{"key":"ref2","article-title":"Si2 High Level Power Modeling Requirements","year":"2014"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2006.1639468"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176629"}],"event":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","location":"Kosice, Slovakia","start":{"date-parts":[[2016,4,20]]},"end":{"date-parts":[[2016,4,22]]}},"container-title":["2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems (DDECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7480193\/7482431\/07482453.pdf?arnumber=7482453","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,24]],"date-time":"2017-06-24T15:36:20Z","timestamp":1498318580000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7482453\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/ddecs.2016.7482453","relation":{},"subject":[],"published":{"date-parts":[[2016,4]]}}}