{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T09:00:41Z","timestamp":1729674041438,"version":"3.28.0"},"reference-count":26,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,4]]},"DOI":"10.1109\/ddecs.2017.7934564","type":"proceedings-article","created":{"date-parts":[[2017,5,29]],"date-time":"2017-05-29T20:22:11Z","timestamp":1496089331000},"page":"35-41","source":"Crossref","is-referenced-by-count":3,"title":["Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test"],"prefix":"10.1109","author":[{"given":"Matthias","family":"Kampmann","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sybille","family":"Hellebrand","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2028679"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2099243"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2015.26"},{"key":"ref13","first-page":"1353","article-title":"An On-Chip Clock Generation Scheme for Faster-than-at-Speed Delay Testing","author":"pei","year":"2010","journal-title":"2010 Design Automation & Test in Europe Conference & Exhibition (DATE 2010)"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700564"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2014.7035360"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271094"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041774"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.863742"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2007.4437576"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2043570"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2013.6651925"},{"key":"ref6","article-title":"Defining faster-than-at-speed delay tests","volume":"2","author":"amodeo","year":"2005","journal-title":"Cadence Nanometer Test Quarterly eNewsletter"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2010.5560326"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"105","DOI":"10.1109\/TEST.2003.1270830","article-title":"Experiments at Detecting Delay Faults using Multiple Higher Frequency Clocks and Results from Neighboring Die","volume":"1","author":"singh","year":"2003","journal-title":"Proceedings 2003 International Test Conference (ITC 2003)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2011.6139131"},{"key":"ref2","first-page":"1291","article-title":"As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization","author":"eggersgl\u00fc\u00df","year":"2011","journal-title":"Design Automation & Test in Europe Conference & Exhibition (DATE)"},{"key":"ref9","first-page":"198","article-title":"A Novel Framework for Faster-than-at-Speed Delay Test Considering IR-drop Effects","author":"ahmed","year":"2006","journal-title":"IEEE\/ACM International Conference on Computer-Aided Design (IC-CAD)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2008.32"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2007.4437575"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2035550"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469617"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2012.6378193"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2016.20"},{"journal-title":"Benchmark information and circuits","year":"2016","key":"ref26"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700646"}],"event":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","start":{"date-parts":[[2017,4,19]]},"location":"Dresden, Germany","end":{"date-parts":[[2017,4,21]]}},"container-title":["2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7932334\/7934552\/07934564.pdf?arnumber=7934564","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,25]],"date-time":"2019-09-25T06:39:34Z","timestamp":1569393574000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7934564\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,4]]},"references-count":26,"URL":"https:\/\/doi.org\/10.1109\/ddecs.2017.7934564","relation":{},"subject":[],"published":{"date-parts":[[2017,4]]}}}