{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T14:58:00Z","timestamp":1730213880701,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,4]]},"DOI":"10.1109\/ddecs.2017.7934575","type":"proceedings-article","created":{"date-parts":[[2017,5,29]],"date-time":"2017-05-29T16:22:11Z","timestamp":1496074931000},"page":"84-87","source":"Crossref","is-referenced-by-count":1,"title":["Energy-aware application-specific topology generation for 3D Network-on-Chips"],"prefix":"10.1109","author":[{"given":"Arash","family":"Barzinmehr","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Suleyman","family":"Tosun","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"Analysis of power consumption on switch fabrics in network routers","author":"ye","year":"2002","journal-title":"DAC"},{"key":"ref11","article-title":"Floorplanning and topology generation for application-specific network-on-chip","author":"yu","year":"2010","journal-title":"Proc of ASP-DAC 2010"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICEP-IAAC.2015.7111027"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-7618-5"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2009.5071456"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.871762"},{"key":"ref3","volume":"35","author":"kim","year":"2007","journal-title":"A novel dimensionally-decomposed router for on-chip communication in 3D architectures ” ACM SIGARCH Computer Architecture News"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-7618-5_8"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090625"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2011.0080"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5937785"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"journal-title":"Computers and Intractability A Guide to the Theory of NP-Completeness","year":"1979","author":"michael","key":"ref9"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382591"}],"event":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","start":{"date-parts":[[2017,4,19]]},"location":"Dresden, Germany","end":{"date-parts":[[2017,4,21]]}},"container-title":["2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7932334\/7934552\/07934575.pdf?arnumber=7934575","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,10,2]],"date-time":"2017-10-02T21:25:16Z","timestamp":1506979516000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7934575\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,4]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/ddecs.2017.7934575","relation":{},"subject":[],"published":{"date-parts":[[2017,4]]}}}