{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T05:23:01Z","timestamp":1729660981700,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,4]]},"DOI":"10.1109\/ddecs.2017.7934576","type":"proceedings-article","created":{"date-parts":[[2017,5,29]],"date-time":"2017-05-29T16:22:11Z","timestamp":1496074931000},"page":"12-15","source":"Crossref","is-referenced-by-count":1,"title":["Improving combinational circuit resilience against soft errors via selective resource allocation"],"prefix":"10.1109","author":[{"given":"Tohid Taghizad Gogjeh","family":"Yaran","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Suleyman","family":"Tosun","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISED.2013.19"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2002.1028924"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2839300"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865418"},{"journal-title":"Synthesis and Optimization of Digital Circuits","year":"1994","author":"micheli","key":"ref11"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2007.25"},{"key":"ref8","first-page":"1258","author":"tosun","year":"2005","journal-title":"Reliability-centric high-level synthesis &#x201D; In Design Automation and Test in Europe"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2015.2440234"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"519","DOI":"10.1145\/2637364.2592000","volume":"42","author":"khan","year":"2014","journal-title":"The efficacy of error mitigation techniques for DRAM retention failures a comparative experimental study In ACM SIGMETRICS Performance Evaluation Review"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2005.15"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/RAMS.2011.5754515"}],"event":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","start":{"date-parts":[[2017,4,19]]},"location":"Dresden, Germany","end":{"date-parts":[[2017,4,21]]}},"container-title":["2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems (DDECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7932334\/7934552\/07934576.pdf?arnumber=7934576","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,25]],"date-time":"2019-09-25T02:39:39Z","timestamp":1569379179000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7934576\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,4]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/ddecs.2017.7934576","relation":{},"subject":[],"published":{"date-parts":[[2017,4]]}}}