{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T14:35:13Z","timestamp":1725460513081},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,4]]},"DOI":"10.1109\/ddecs.2017.7934586","type":"proceedings-article","created":{"date-parts":[[2017,5,29]],"date-time":"2017-05-29T20:22:11Z","timestamp":1496089331000},"page":"54-59","source":"Crossref","is-referenced-by-count":0,"title":["Logic testing with test-per-clock pattern loading and improved diagnostic abilities"],"prefix":"10.1109","author":[{"given":"Ondrej","family":"Novak","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zdenek","family":"Pliva","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2008.4538794"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894274"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/11408901_30"},{"key":"ref6","article-title":"LFSR - coded test patterns for scan designs","author":"koenemann","year":"1991","journal-title":"Proc Europ Test Conf"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ETW.2002.1029637"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/12.214664"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2014.6847822"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-009-5107-5"},{"key":"ref7","article-title":"Diagnostic logic testing based on advanced scan technology and an embedded test processor","author":"kothe","year":"2007","journal-title":"Report 01\/07 of Brandenburg University of Technology at Cottbus"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2006.297720"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1023\/B:JETT.0000009317.31947.c8"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2011.25"}],"event":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","start":{"date-parts":[[2017,4,19]]},"location":"Dresden, Germany","end":{"date-parts":[[2017,4,21]]}},"container-title":["2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7932334\/7934552\/07934586.pdf?arnumber=7934586","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,5]],"date-time":"2017-06-05T18:56:21Z","timestamp":1496688981000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7934586\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,4]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/ddecs.2017.7934586","relation":{},"subject":[],"published":{"date-parts":[[2017,4]]}}}