{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T04:15:45Z","timestamp":1725596145597},"reference-count":27,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,4]]},"DOI":"10.1109\/ddecs.2019.8724637","type":"proceedings-article","created":{"date-parts":[[2019,5,30]],"date-time":"2019-05-30T22:52:12Z","timestamp":1559256732000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["Generic Error Localization for the Electronic System Level"],"prefix":"10.1109","author":[{"given":"Sebastian","family":"Pointner","sequence":"first","affiliation":[]},{"given":"Pablo Gonzalez","family":"de Aledo","sequence":"additional","affiliation":[]},{"given":"Robert","family":"Wille","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Cause Clue Clauses Error Localization Using Maximum Satisfiability","year":"2010","author":"jose","key":"ref10"},{"key":"ref11","article-title":"Automated error localization and correction for imperative programs","author":"k\u00f6nighofer","year":"2011","journal-title":"Int'l Conf on Formal Methods in CAD"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/604131.604140"},{"key":"ref13","doi-asserted-by":"crossref","DOI":"10.1109\/FDL.2008.4641434","article-title":"Contradiction Analysis for Constraint-based Random Simulation","author":"gro\u00dfe","year":"2008","journal-title":"Forum on Specification and Design Languages"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2015.52"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.2009.28"},{"key":"ref16","article-title":"Program slicing","author":"weiser","year":"1981","journal-title":"Proc Int l Conf Software Engineering"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ASE.2011.6100114"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TSE.1976.233817"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/360248.360252"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2005.1465549"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ICSE.1994.296778"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSoC.2012.6376356"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-46681-0_36"},{"key":"ref5","article-title":"KLEE: Unassisted and Automatic Generation of High-Coverage Tests for Complex Systems Programs","author":"cadar","year":"2008","journal-title":"Proceedings of Operating System Design and Implementation"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744921"},{"key":"ref7","first-page":"475","article-title":"Towards a Verification Flow Across Abstraction Levels: Verifying Implementations Against Their Formal Specification","author":"gonzales de aledo","year":"2017","journal-title":"IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems"},{"key":"ref2","article-title":"SMT-based Stimuli Generation in the SystemC Verification Library","author":"wille","year":"2009","journal-title":"Forum on Specification and Design Languages"},{"journal-title":"FoREnSiC- An Automatic Debugging Environment for C Programs","year":"2012","author":"bloem","key":"ref9"},{"journal-title":"ESL Design and Verification A Prescription for Electronic System Level Methodology","year":"2007","author":"martin","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MS.2017.3571576"},{"key":"ref22","article-title":"Behavioral Consistency of C and Verilog Programs Using Bounded Model Checking","author":"kroening","year":"2003","journal-title":"Processings of the DA Conf"},{"key":"ref21","article-title":"The auspicious couple: Symbolic execution and WCET analysis","author":"biere","year":"2013","journal-title":"OASlcs-OpenAccess Series in Informatics"},{"key":"ref24","article-title":"Z3: An efficient SMT Solver","author":"de moura","year":"2008","journal-title":"Tools and Algorithms for the Construction and Analysis of Systems"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2232351"},{"journal-title":"Why Programs Fail A Guide to Systematic Debugging","year":"2005","author":"zeller","key":"ref26"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2004.1281665"}],"event":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","start":{"date-parts":[[2019,4,24]]},"location":"Cluj-Napoca, Romania","end":{"date-parts":[[2019,4,26]]}},"container-title":["2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems (DDECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8718445\/8724630\/08724637.pdf?arnumber=8724637","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,19]],"date-time":"2022-07-19T20:21:44Z","timestamp":1658262104000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8724637\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,4]]},"references-count":27,"URL":"https:\/\/doi.org\/10.1109\/ddecs.2019.8724637","relation":{},"subject":[],"published":{"date-parts":[[2019,4]]}}}